Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method

ABSTRACT

In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device includingmetal wiring layers such as copper (Cu) wiring layers and itsmanufacturing method.

[0003] 2. Description of the Related Art

[0004] As semiconductor devices have been become more-finely structured,the resistance of wiring layers have been increased, and also, theparasitic capacitance therebetween has been increased. Note that theincrease of resistance and the increase of parasitic capacitance inwiring layers increase time-constants thereof, which would delay thepropagation of signals on the wiring layers.

[0005] In order to decrease the resistance of wiring layers, use is madeof Cu rather than aluminum (Al). However, since it is difficult tosubject Cu to a dry etching process, a chemical mechanical polishing(CMP) process is applied to the formation of wiring layers using Cu,which is called a damascene structure.

[0006] In a prior art method for manufacturing a single-damascenestructure using Cu (see: JP-A-2000-150517), a copper layer filled in agroove of an insulating interlayer by a CMP process is completelysandwiched by a barrier metal layer and a copper diffusion barrierlayer, so as to suppress the oxidation of the copper layer and diffusionof copper from the copper layer. Also, in order to suppress theelectromigration of the copper layer, a Cu silicide is formed on theupper surface of the copper layer. This will be explained later indetail.

[0007] In the above-described prior art method for a single-damascenestructure, however, the resistance of wiring layers is substantiallyincreased due to the presence of Cu silicide and the oxide thereon.

[0008] On the other hand, in a prior art method for manufacturing adual-damascene structure using Cu, a first copper layer is filled in agroove of an insulating interlayer via a barrier metal layer, and then,a copper diffusion barrier layer is formed thereon. Then, insulatinginterlayers are further formed on the copper diffusion barrier layer,and a via hole is formed in the insulating interlayers by aphotolithography and etching process using the copper diffusion barrierlayer as an etching stopper. Then, another copper layer is filled in thevia hole and is connected to the first copper layer. This also will beexplained later in detail.

[0009] In the above-described prior art method for a dual-damascenestructure, however, the copper diffusion barrier layer may be overetchedby the photolithography and etching process for the insulatinginterlayers, so that the first copper layer is oxidized by thepost-stage dry ashing process using O₂ gas plasma, which decreases themanufacturing yield and enhances the electromigration.

[0010] Note that the dual-damascene structure is mainly divided into avia first type; a middle first type; and a trench first type.

[0011] In the via first type dual damascene structure, first and secondinsulating layers are sequentially formed. Then, a via hole is formed inthe first insulating interlayer, and then, a groove is formed in thesecond insulating interlayer. Finally, a via structure and a groovewiring layer are simultaneously formed in the via hole and the groove,respectively.

[0012] In the middle first type dual-damascene structure, a firstinsulating interlayer is formed, and a via hole etching mask is formedon the first insulating interlayer. Then, a second insulating interlayer is formed. Then, a groove is formed in the second insulatinginterlayer simultaneously with the formation of a via hole in the firstinsulating interlayer using the via hole as an etching mask. Finally, avia structure and a groove wiring layer are simultaneously formed in thevia hole and the groove, respectively. In the middle first typedual-damascene structure, note that anti-reflective layers forsuppressing reflective light from an under Cu layer cannot be used inthe photolithography processes for the formation of the via hole maskand the groove.

[0013] In the trench first type dual-damascene structure, first andsecond insulating interlayers are sequentially formed. Then, a groove(trench) is formed in the second insulating interlayer. Then, a via holeis formed in the first insulating interlayer. Finally, a via structureand a groove wiring layer are simultaneously formed in the via hole andthe groove, respectively. In the trench first type dual-damascenestructure, note that an anti-reflective layer for suppressing reflectivelight from an under Cu layer cannot be used in the photolithographyprocess for the formation of the via hole.

[0014] The via first type dual-damascene structure is used for finerlower wiring layers, while the middle first type and the trench firsttype dual-damascene structures are used for non-fine middle and upperwiring layers.

SUMMARY OF THE INVENTION

[0015] It is an object of the present invention to provide asingle-damascene type semiconductor device and its manufacturing methodhaving a wiring layer capable of substantially decreasing the resistancethereof.

[0016] Another object of the present invention is to provide adual-damascene type semiconductor device and its manufacturing methodcapable of increasing the manufacturing yield.

[0017] According to the present invention, a semiconductor device isconstructed by an insulating underlayer; a first insulating interlayerformed on the insulating underlayer and having a groove; a firstsilicon-diffused metal layer buried in the groove; and a first metaldiffusion barrier layer formed on the first silicon-diffused metal layerand the first insulating interlayer.

[0018] The semiconductor device is further constructed by a secondinsulating interlayer formed on the first metal diffusion barrier layer,the second insulating interlayer and the first metal diffusion barrierlayer having a via hole opposing the groove of the first insulatinginterlayer; a second silicon-diffused metal layer buried in the viahole; a second metal diffusion barrier layer formed on the secondsilicon-diffused metal layer and the second insulating interlayer; athird insulating interlayer formed on the second metal diffusion barrierlayer, the third insulating interlayer and the second metal diffusionbarrier layer having a trench opposing the via hole; a thirdsilicon-diffused metal layer buried in the trench; and a third metaldiffusion barrier layer formed on the third silicon-diffused metal layerand the third insulating interlayers. Thus, a multiple-layersingle-damascene structure is obtained.

[0019] On the other hand, the semiconductor device is furtherconstructed by a second insulating interlayer formed on the first metaldiffusion barrier layer, the second insulating interlayer and the firstmetal diffusion barrier layer having a via hole opposing the groove ofthe first insulating interlayer; a third insulating interlayer formed onthe second insulating interlayer, the third insulating interlayer havinga trench opposing the via hole; a second silicon-diffused metal layerburied in the trench and via hole; and a second metal diffusion barrierlayer formed on the second silicon-diffused metal layer and the thirdinsulating interlayer. Thus, a dual-damascene structure is obtained.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be more clearly understood from thedescription set forth below, as compared with the prior art, withreference to the accompanying drawings, wherein:

[0021]FIGS. 1A through 1H are cross-sectional views for explaining afirst prior art method for manufacturing a semiconductor device;

[0022]FIGS. 2A through 2P are cross-sectional views for explaining asecond prior art method for manufacturing a semiconductor device;

[0023]FIG. 3 is a graph showing the manufacturing yield of the viastructure obtained by the method as illustrated in FIGS. 2A through 2P;

[0024]FIG. 4 is a cross-sectional view illustrating a conventionalparallel-plate type plasma chemical vapor deposition (CVD) apparatus;

[0025]FIGS. 5A through 5J are cross-sectional views for explaining afirst embodiment of the method for manufacturing a semiconductor deviceaccording to the present invention;

[0026]FIG. 6 is a graph showing the Si component distribution within thesilicon-diffused copper layer of FIG. 5I;

[0027]FIG. 7 is a phase diagram of Cu-Si;

[0028]FIG. 8A is a graph showing Cu silicide generation characteristicsof FIG. 5H;

[0029]FIG. 8B is a graph shown BTA removal amount characteristics ofFIG. 5H;

[0030]FIG. 8C is a table showing the presence or absence of Si in thesilicon-diffused copper layer of FIG. 5H;

[0031]FIGS. 9A through 9S are cross-sectional views for explaining asecond embodiment of the method for manufacturing a semiconductor deviceaccording to the present invention;

[0032]FIGS. 10A through 10V are cross-sectional views for explaining athird embodiment of the method for manufacturing a semiconductor deviceaccording to the present invention;

[0033]FIG. 11 is a graph showing the failure possibility characteristicsof the semiconductor device obtained by the method as illustrated inFIGS. 10A through 10V;

[0034]FIG. 12 is a graph showing the manufacturing yield characteristicsof the semiconductor device obtained by the method as illustrated inFIGS. 10A through 10V;

[0035]FIGS. 13A through 13F are cross-sectional views for explaining afourth embodiment of the method for manufacturing a semiconductor deviceaccording to the present invention;

[0036]FIG. 14 is a graph showing reflectivity characteristics of pure Cuand silicon-diffused Cu;

[0037]FIGS. 15A through 15F are cross-sectional views for explaining afifth embodiment of the method for manufacturing a semiconductor deviceaccording to the present invention;

[0038]FIG. 16A is a diagram showing a chemical structure of ladder-typehydrogen siloxane;

[0039]FIG. 16B is a table showing the characteristics of the ladder-typehydrogen siloxane of FIG. 16A;

[0040]FIG. 16C is a graph showing the absorbance characteristics of theladder-type hydrogen siloxane of FIG. 16A;

[0041]FIG. 16D is a graph showing the density and infractive indexcharacteristics of the ladder-type hydrogen siloxane of FIG. 16A;

[0042]FIG. 17 is a diagram showing a chemical structure of hydrogensilsesquioxane (HSQ);

[0043]FIGS. 18, 19 and 20 are graphs showing the characteristics of theladder-type hydrogen siloxane according to the present invention andhydrogen silsesquioxane (HSQ);

[0044]FIG. 21A is a diagram of a semiconductor wafer; and

[0045]FIG. 21B is a table showing the etching amounts of the ladder-typehydrogen siloxane and HSQ on the semiconductor wafer of FIG. 21A.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] Before the description of the preferred embodiments, prior artmethods for manufacturing a semiconductor device will be explained withreference to FIGS. 1A through 1H and FIGS. 2A through 2P, and 3.

[0047]FIGS. 1A through 1H are cross-sectional views for explaining afirst prior art method for a manufacturing a semiconductor device (see:JP-A-2000-150517). In this case, a one-layer single-damascene structureis formed.

[0048] First, referring to FIG. 1A, an insulating underlayer 101 made ofsilicon dioxide or the like is formed on a silicon substrate (not shown)where various semiconductor elements are formed. Then, an etchingstopper 102 made of SiCN is formed by a plasma CVD process on theinsulating layer 101. Then, an insulating interlayer 103 made of silicondioxide is deposited by a CVD process on the etching stopper 102. Then,an anti-reflective coating layer 104 and a photoresist layer 105 aresequentially coated on the insulating interlayer 103. Then, thephotoresist layer 105 is patterned by a photolithography process, sothat a groove 105 a is formed in the photoresist layer 105.

[0049] Next, referring to FIG. 1B, the anti-reflective coating layer 104and the insulating interlayer 103 are etched by a dry etching processusing the photoresist layer 105 as a mask.

[0050] Next, referring to FIG. 1C, the photoresist layer 105 and theanti-reflective layer 104 are ashed by a dry ashing process using O₂ gasplasma.

[0051] Next, referring to FIG. 1D, the etching stopper 102 is etchedback by a dry etching process. Then, a wet stripping process isperformed upon the insulating interlayer 103 and the insulatingunderlayer 101, so that residues of the dry etching process arecompletely removed.

[0052] Next, referring to FIG. 1E, a barrier metal layer 106 made of Taon TaN and a seed copper layer 107 a are sequentially deposited by asputtering process on the entire surface. Then, a copper layer 107 b isfurther deposited by an electroplating process using the seed copperlayer 107 a as a cathode electrode. Note that the copper layers 107 aand 107 b form a copper layer 107. Then, an annealing treatment isperformed upon the copper layer 107 under a N₂ atmosphere to crystallizethe copper layer 107.

[0053] Next, referring to FIG. 1F, the copper layer 107 and the barriermetal layer 106 on the insulating interlayer 103 are removed by a CMPprocess.

[0054] Next, referring to FIG. 1G, a Cu silicide layer 108 is grown inthe copper layer 107 by a passivation process using SiH₄ gas.

[0055] Finally, referring to FIG. 1H, a copper diffusion barrier layer109 made of SiN is deposited on the entire surface by a plasma CVDprocess using SiH₄ gas. Then, an insulating interlayer 110 made ofsilicon dioxide is formed on the copper diffusion barrier layer 109.

[0056] In the first prior art method as illustrated in FIGS. 1A through1H, in order to suppress the oxidation of the copper layer 107 and thediffusion of copper from the copper layer 107 to the insulatingunderlayer 101 and the insulating interlayers 103 and 110 made ofsilicon dioxide, the copper layer 107 is completely surrounded by thebarrier metal layer 106 and the copper diffusion barrier layer 109.

[0057] Also, in the first prior art method as illustrated in FIGS. 1Athrough 1H, in order to suppress the electromigration of the copperlayer 107, the Cu silicide layer 108 is formed on the upper surface ofthe copper layer 107.

[0058] In the first prior art method as illustrated in FIGS. 1A through1H, since the resistivity of Cu silicide is higher than that of Cu, theresistance of a wiring layer made of Cu and Cu silicide is substantiallyincreased. Also, when a via hole is formed in the insulating interlayer110, a part of the Cu silicide layer 108 may be removed. Therefore, inview of this, in order to surely suppress the electromigration andstress migration, the Cu silicide layer 108 has to be even thicker,which also substantially increases the resistance of the wiring layermade of Cu and Cu silicide. Further, if the copper layer 107 is oxidizedbefore the growth of the Cu silicide layer 108, the oxide of Cu willreact with silicon in a SiH₄ gas atmosphere, so that mixture of Cu, Siand O abnormally grow, which also substantially increases the resistanceof the wiring layer. At worst, the mixture of Cu, Si and O grown at theperiphery of the wiring layer and the barrier metal layer 106 invites ashort-circuit between two adjacent wiring layers, if they are close toeach other.

[0059] On the other hand, in order to decrease the parasitic capacitancebetween wiring layers, the copper diffusion barrier layer 109 can bemade of SiC or SiCN which has a lower dielectric constant than that ofSiN. That is, the copper diffusion barrier layer 109 can be deposited bya plasma CVD process using organic silane gas such as SiH(CH₃)₃ gas orSi(CH₃)₄ gas, not SiH₄ gas. In this case, bonding energy between Si andan organic group in SiH(CH₃)₃ or Si(CH₃)₄ is stronger than bondingenergy between Si and H in SiH₄, so that thermal decomposition ofSiH(CH₃)₃ or Si(CH₃)₄ is harder than thermal decomposition of SiH₄. As aresult, Cu silicide is hardly grown by using SiH(CH₃)₃ gas or Si(CH₃)₄gas as compared with SiH₄ gas. Note that, if there is no Cu silicidebetween the copper layer 107 and the Cu diffusion barrier layer 109 madeof SiCN, the contact characteristics therebetween deteriorate, so thatthe crystal grains of the copper layer 107 are not stabilized, whichwould decrease the electromigration resistance and also, would decreasethe stress migration resistance so that the copper layer 107 is easilybroken.

[0060]FIGS. 2A through 2P are cross-sectional views for explaining asecond prior art method for manufacturing a semiconductor device. Inthis case, a two-layer via first type dual-damascene structure isformed.

[0061] First, referring to FIG. 2A, an insulating underlayer 201 made ofsilicon dioxide or the like is formed on a silicon substrate (not shown)where various semiconductor elements are formed. Then, an etchingstopper 202 made of SiN is formed by a plasma CVD process on theinsulating layer 201. Then, an insulating interlayer 203 made of silicondioxide is deposited by a CVD process on the etching stopper 202. Then,an anti-reflective coating layer 204 and a photoresist layer 205 aresequentially coated on the insulating interlayer 203. Then, thephotoresist layer 205 is patterned by a photolithography process, sothat a groove 205 a is formed in the photoresist layer 205.

[0062] Next, referring to FIG. 2B, the anti-reflective coating layer 204and the insulating interlayer 203 are etched by a dry etching processusing the photoresist layer 205 as a mask.

[0063] Next, referring to FIG. 2C, the photoresist layer 205 and theanti-reflective layer 204 are ashed by a dry ashing process using O₂ gasplasma.

[0064] Next, referring to FIG. 2D, the etching stopper 202 is etchedback by a dry etching process. Then, a wet stripping process isperformed upon the insulating interlayer 203 and the insulatingunderlayer 201, so that residues of the dry etching process arecompletely removed.

[0065] Next, referring to FIG. 2E, a barrier metal layer 206 made of Taon TaN and a seed copper layer 207 a are sequentially deposited by asputtering process on the entire surface. Then, a copper layer 207 b isfurther deposited by an electroplating process using the seed copperlayer 207 a as a cathode electrode. Note that the copper layers 207 aand 207 b form a copper layer 207. Then, an annealing treatment isperformed upon the copper layer 207 under a N₂ atmosphere to crystallizethe copper layer 207.

[0066] Next, referring to FIG. 2F, the copper layer 207 and the barriermetal layer 206 on the insulating interlayer 203 are removed by a CMPprocess.

[0067] Next, referring to FIG. 2G, a copper diffusion barrier layer 208made of SiCN, an insulating interlayer 209 made of silicon dioxide, anetching stopper 210 made of SiCN, and an insulating interlayer 211 madeof silicon dioxide are sequentially deposited on the entire surface.Then, an anti-reflective layer 212 and a photoresist layer 213 aresequentially coated on the insulating interlayer 211. Then, thephotoresist layer 213 is patterned by a photolithography process, sothat a via hole 213 a is formed in the photoresist layer 213.

[0068] Next, referring to FIG. 2H, the anti-reflective layer 212 and theinsulating interlayer 211, the etching stopper 210 and the insulatinginterlayer 209 are etched by a dry etching process using CF based gasplasma and using the copper diffusion barrier layer 208 as an etchingstopper. In this case, since the copper diffusion barrier layer 208 isan incomplete etching stopper, the copper diffusion barrier layer 208may be also etched as indicated by X.

[0069] Next, referring to FIG. 21, the photoresist layer 213 and theanti-reflective layer 212 are ashed by a dry ashing process using O₂ gasplasma. In this case, an exposed portion of the copper layer 207 isoxidized, so that a copper oxide layer 207 c is grown in the copperlayer 207.

[0070] Next, referring to FIG. 2J, an anti-reflective layer 214 and aphotoresist layer 215 are sequentially coated on the entire surface.Then, the photoresist layer 215 is patterned by a photolithographyprocess so that a groove 215 a is formed in the photoresist layer 215.In this case, the anti-reflective layer 214 is buried in the via hole213 a.

[0071] Next, referring to FIG. 2K, the insulating interlayer 211 and theetching stopper 210 are etched by a dry etching process using CF basedgas plasma and using the photoresist layer 215 as a mask.

[0072] Next, referring to FIG. 2L, the photoresist layer 215 and theanti-reflective layer 214 are ashed by a dry ashing process using O₂ gasplasma. In this case, the copper oxide layer 207 c is further grown inthe copper layer 207.

[0073] Next, referring to FIG. 2M, the copper diffusion-barrier layer208 is etched back by a dry etching process. Then, a wet strippingprocess is performed upon the insulating interlayer 211, the etchingstopper 210, the insulating interlayer 209 and the copperdiffusion-barrier layer 208, so that residues of the dry etching processare completely removed.

[0074] Next, referring to FIG. 2N, a barrier metal layer 216 made of Taon TaN and a seed copper layer 217 a are sequentially deposited by asputtering process on the entire surface. Then, a copper layer 217 b isfurther deposited by an electroplating process using the seed copperlayer 217 a as an cathode electrode. Note that the copper layers 217 aand 217 b form a copper layer 217. Then, an annealing treatment isperformed upon the copper layer 217 under a N₂ atmosphere to crystallizethe copper layer 217.

[0075] Next, referring to FIG. 20, the copper layer 217 and the barriermetal layer 216 on the insulating interlayer 211 are removed by a CMPprocess.

[0076] Finally, referring to FIG. 2P, a copper diffusion barrier layer218 made of SiCN is deposited by a plasma CVD process.

[0077] In the method as illustrated in FIGS. 2A through 2P, when thecopper diffusion barrier layer 208 is overetched, the copper layer 207is oxidized by the dry ashing process using O₂ gas plasma, whichdecreases the manufacturing yield of the via structure and enhances theelectromignation of the via structure. If the photolightography andetching process for the insulating interlayers 211 and 209 fails,photolithography and etching processes for the insulating interlayers211 and 209 are repeated. In this case, since the copper layer 207 isfurther oxidized by the dry ashing process using O₂ gas plasma, themanufacturing yield of the via structure is further decreased as shownin FIG. 3. This is true for a middle-first type dual-damascene structureand a trench-first type dual-damascene structure.

[0078]FIG. 4 illustrates a conventional parallel-plate type plasma CVDapparatus which is used in the manufacture of a semiconductor deviceaccording to the present invention, reference numeral 41 designates aprocessing chamber where a plurality of reaction gases are supplied froma gas supply section 42 via a gas flow rate controller 43 and a reactedgas is exhausted by a gas exhaust section 44, so that the pressure inthe processing chamber 41 is controlled to be definite. The processingchamber 41 is provided with an upper plate electrode 45 and a lowerplate electrode 46 to which a radio frequency (RF) power is applied froman RF source 47. A lower surface of the electrode 46 is fixed on aheater 48, while an upper surface of the electrode 46 is used formounting a semiconductor wafer 49. The gas flow rate controller 43, thegas exhaust section 44, the RF source 47 and the heater 48 arecontrolled by a computer 50.

[0079] For example, when depositing a SiN layer on the semiconductorwafer 49, SiH₄ gas, NH₃ gas and N₂ gas are supplied from the gas supplysection 42 via the gas flow rate controller 43 controlled by thecomputer 50 to the processing chamber 41. Also, the heater 48 iscontrolled by the computer 50, so that the temperature in the processingchamber 41 is caused to be a predetermined value. Further, apredetermined RF power is supplied by the RF power source 47 controlledby the computer 50. Additionally, the gas exhaust section 44 iscontrolled by the computer 50, so that the processing pressure is causedto be a predetermined value.

[0080]FIGS. 5A through 5J are cross-sectional views for explaining afirst embodiment of the method for manufacturing a semiconductor deviceaccording to the present invention. In this case, a one-layersingle-damascene structure is formed.

[0081] First, referring to FIG. 5A, in the same way as in FIG. 1A, aninsulating under layer 101 made of silicon dioxide or the like is formedon a silicon substrate (not shown) where various semiconductor elementsare formed. Then, an about 50 nm thick etching stopper 102 made of SiCNis formed by a plasma process on the insulating layer 101. Then, anabout 400 nm thick insulating interlayer 103 made of silicon dioxide isdeposited by a plasma CVD process on the etching stopper 102. Then, ananti-reflective coating layer 104 and a photoresist layer 105 aresequentially coated on the insulating interlayer 103. Then, thephotoresist layer 105 is patterned by a photolithography process, sothat a groove 105 a is formed in the photoresist layer 105. Note thatthe insulating interlayer 103 can be made of a low-k material having alower dielectric constant than that of silicon dioxide.

[0082] Next, referring to FIG. 5B, in the same way as in FIG. 1B, theanti-reflective coating layer 104 and the insulating interlayer 103 isetched by a dry etching process using the photoresist layer 105 as amask.

[0083] Next, referring to FIG. 5C, in the same way as in FIG. 1C, thephotoresist layer 105 and the anti-reflective layer 104 are ashed by adry ashing process using O₂ gas plasma.

[0084] Next, referring to FIG. 5D, in the same way as in FIG. 1D, theetching stopper 102 is etched back by a dry etching process. Then, a wetstripping process is performed upon the insulating interlayer 103 andthe insulating underlayer 101, so that residues of the dry etchingprocess is completely removed.

[0085] Next, referring to FIG. 5E, in the same way as in FIG. 1E, anabout 30 nm thick barrier metal layer 106 made of Ta on TaN and an about100 nm thick seed copper layer 107 a are sequentially deposited by asputtering process on the entire surface. Then, an about 700 nm thickcopper layer 107 b is further deposited by an electroplating processusing the seed copper layer 107 a as a cathode electrode. Note that thecopper layers 107 a and 107 b form a copper layer 107. Then, anannealing treatment is performed upon the copper layer 107 under a N₂atmosphere to crystallize the copper layer 107 at a temperature of about400° C. for about 30 minutes.

[0086] Next, referring to FIG. 5F, in the same way as in FIG. 1F, thecopper layer 107 and the barrier metal layer 106 on the insulatinginterlayer 103 are removed by a CMP process.

[0087] Next, referring to FIG. 5G, the semiconductor device is cleanedand rinsed. In this case, since Cu oxide (not shown) is grown on thecopper layer 107 by pure water, the Cu oxide is removed by a solution ofoxalic acid. Then, the semiconductor device is immersed into a 1%diluted solution of benzotriazole (BTA). As a result, BTA reacts withthe Cu oxide, so that a BTA layer 107 a serving as an oxidation barrierlayer is formed on the copper layer 107. Note that the step of removingthe Cu oxide by oxalic acid can be deleted.

[0088] Next, referring to FIG. 5H, the semiconductor device is put intothe plasma CVD apparatus of FIG. 4. Then, in the plasma CVD apparatus ofFIG. 4, a heating process is performed upon the BTA layer 107 a for 2minutes under the following conditions:

[0089] temperature: 250 to 400° C.

[0090] N₂ gas: 0 to 5000 sccm

[0091] processing pressure: 0 to 20 Torr (0 to 2666.4 Pa).

[0092] As a result, the BTA layer 107 a is thermally decomposed andremoved. In this case, the copper layer 107 includes no Cu silicide.

[0093] Subsequently, in the plasma CVD apparatus of FIG. 4, a heatingprocess is performed upon the copper layer 107 for 120 seconds under thefollowing conditions:

[0094] temperature: 250 to 400° C.

[0095] SiH₄ gas: 10 to 1000 sccm

[0096] N₂ (or Ar, He etc.) gas: 0 to 5000 sccm

[0097] processing pressure: 0 to 20 Torr (0 to 2666.4 Pa).

[0098] Thus, the copper layer 107 is converted into a silicon-diffusedcopper layer 111. Note that inorganic silane gas such as Si₂H₆ gas orSiH₂Cl₂ can be used instead of SiH₄ gas under the conditions that thetemperature is 250 to 400° C. and the processing pressure is less than20 Torr (2666 Pa), to decrease the processing time. Then, in the plasmaCVD apparatus of FIG. 4, as occasion demands, a plasma process isfurther performed upon the silicon-diffused copper layer 111 and theinsulating interlayer 103 for 3 seconds under the following conditions:

[0099] NH₃ gas: 10 to 1000 sccm

[0100] N₂ gas: 0 to 5000 sccm

[0101] processing pressure: 1 to 20 Torr (133.3 to 2666.4 Pa)

[0102] high frequency wave at 100 kHz to 13.56 MHz

[0103] RF power: 50 to 500W.

[0104] Thus, silicon (not shown) on the surfaces of the silicon-diffusedcopper layer 111 and the insulating interlayer 103 is nitrized. Notethat the silicon on the surfaces can also be etched by a plasma processusing Ar (or He) gas.

[0105] In FIG. 5H, note that at least one of NH₃ gas, H₂ gas, He gas, Argas and SiH₄ gas without O₂ gas can be used instead of N₂ gas. That is,NH₃ gas or H₂ gas react with remainder Cu oxide between the copper layer107 and the BTA layer 107 a, so as to remove the remainder Cu oxide.Further, a heat treatment at 250 to 400° C. and a pressure of less than20 Torr (2666 Pa) without any gas can remove the BTA layer 107 a. Notethat this plasma process is carried out at a temperature of 250 to 400°C., at a processing pressure less than 20 Torr (2666 Pa) and at an RFpower of 50 to 500W.

[0106] Note that, after the BTA layer 107 a is formed as illustrated inFIG. 5G and before the heating process as illustrated in FIG. 5H iscarried out, if Cu oxide on the copper layer 107 is removed by reducingit by reducing gas plasma treatment using H₂ gas or NH₃ gas, the growthof Cu silicide is enhanced, which is not preferable. On the other hand,after the heating process as illustrated in FIG. 5H is carried out, ifCu oxide on the silicon-diffused copper layer 111 is removed by reducinggas plasma treatment using H₂ gas or NH₃ gas, there is no effect on thegrowth of Cu silicide, so that no problem occurs.

[0107] Next, referring to FIG. 51, in the plasma CVD apparatus of FIG.4, a plasma process is carried out under the following conditions:

[0108] SiH (CH₃)₃ gas: 10 to 1000 sccm

[0109] NH₃ gas: 10 to 500 sccm

[0110] He gas: 0 to 5000 sccm

[0111] processing pressure: 1 to 20 Torr (133.3 to 2666.4 Pa)

[0112] high frequency wave at 100 kHz to 13.56 MHz

[0113] RF power: 50 to 500 W.

[0114] Thus, an about 50 nm thick copper diffusion barrier layer 109made of SiCN is deposited on the entire surface. In this case, thesilicon on an upper side of the silicon-diffused copper layer 111diffuses deeply thereinto. As a result, the Si component distributionwithin the silicon-diffused copper layer 111 is shown in FIG. 6 where aninsulating underlayer (SiO₂) is in direct contact with asilicon-diffused copper layer. That is, the deeper the location of thesilicon-diffused copper layer 111, the smaller the concentration of Si.As a result, the contact characteristics between the silicon-diffusedcopper layer 111 and the copper diffusion barrier layer 109 can beimproved. Also, the ratio of silicon component to copper component iscaused to be lower than 8 atoms %, so that no Cu silicide having a largeresistance is generated (see Cu-Si phase diagram of FIG. 7).

[0115] Note that the copper diffusion barrier layer 109 can be made ofSiC, SiCN, SiOC or organic material such as benzocycrobutene by a plasmaprocess in the plasma CVD apparatus of FIG. 4. Also, the copperdiffusion barrier layer 109 can be a multiple layer of SiC, SiCN, SiOCand the above-mentioned organic material.

[0116] Finally, referring to FIG. 5J, an about 500 nm thick insulatinginterlayer 110 made of silicon dioxide is formed on the copper diffusionbarrier layer 109. Note that the insulating interlayer 110 can be madeof a low-k material having a lower dielectric constant than that ofsilicon dioxide.

[0117] In the method as illustrated in FIGS. 5A through 5J, since thethree processes as illustrated in FIGS. 5H and 51 are sequentiallycarried out in the plasma CVD apparatus of FIG. 4 without exposing thesemiconductor device to the air, no oxide is grown between thesilicon-diffused copper layer 111 and the copper diffusion barrier layer109.

[0118] Also, since silicon is diffused into the entirety of thesilicon-diffused copper layer 111, the migration of copper atoms withinthe silicon-diffused copper layer 111 can be suppressed. Additionally,since the total amount of silicon in the silicon-diffused copper layer111 is smaller than the total amount of silicon in the Cu silicide layer108 of FIG. 111, the increase of resistance in the wiring layer, i.e.,the silicon-diffused copper layer 111 can be suppressed. Further, at apost stage, even if the silicon-diffused copper layer 111 is etched byan etching process, since silicon is present on the etched surface, theoxidation of the silicon-diffused copper layer 111 is suppressed, whichwould increase the manufacturing yield.

[0119] The temperature range of the heating processes carried out asshown FIG. 5H will be explained next with reference to FIGS. 8A, 8B and8C.

[0120] The reason why the upper limit of the temperature is 400° C. isexplained with reference to FIG. 8A which shows Cu silicide generationcharacteristics of FIG. 5H. That is, when the temperature is lower thanabout 400° C., no Cu silicide is grown on the silicon-diffused copperlayer 111. However, when the temperature is 425° C., Cu silicide ispartially grown on the silicon-diffused copper layer 111. Further, whenthe temperature is 450° C., a lot of Cu silicide is grown on thesilicon-diffused copper layer 111. Note that, in the prior art method asillustrated in FIG. 1G, even when the temperature is 250° C., a lot ofCu silicide is grown on the copper layer 107 of FIG. 1G.

[0121] The reason why the lower limit of the temperature is about 250°C. is explained with reference to FIG. 8B which shows BTA removalcharacteristics of FIG. 5H. That is, when the temperature is 180° C.,the BTA layer 107 a starts to be removed. Also, when the temperature is250° C. the removal circuit the BTA layer 107 a reaches its maximum.

[0122] Also, referring to FIG. 8C, which shows the presence or absenceof Si in the layer 111 of FIG. 5H executed by using an atmosphericpressure ion-mass spectroscopy (API-MS) method, when the temperature is200° C. or 225° C., no Si is observed in the layer 111. On the otherhand, when the temperature is 250° C., 300° C., 350° C. or 400° C., Siis observed in the layer 111.

[0123] Thus, at a step as illustrated in FIG. 5H, when the heatingprocess is carried out at a temperature from 250 to 400° C., the copperlayer 107 is converted into the silicon-diffused copper layer 111 whilethe BTA layer 107 a is completely removed, thus enhancing thethroughput.

[0124]FIGS. 9A through 9S are cross-sectional views for explaining asecond embodiment of the method for manufacturing a semiconductor deviceaccording to the present invention. In this case, a two-layersingle-damascene structure is formed.

[0125] Assume that the semiconductor device as illustrated in FIG. 5J iscompleted. In this case, the silicon-diffused copper layer 111 serves asa lower wiring layer.

[0126] Next, referring to FIG. 9A, an anti-reflective coating layer 131and a photoresist layer 132 are sequentially coated on the insulatinginterlayer 110. Then, the photoresist layer 132 is patterned by aphotolithography process, so that a via hole 132 a is formed in thephotoresist layer 132.

[0127] Next, referring to FIG. 9B, the insulating interlayer 110 and theanti-reflective coating layer 131 is etched by a dry etching processusing the photoresist layer 132 as a mask. In this case, since thecopper diffusion barrier layer 109 is an incomplete etching stopper, thecopper diffusion barrier layer 109 may be also etched as indicated by X.

[0128] Next, referring to FIG. 9C, the photoresist layer 132 and theanti-reflective layer 131 are ashed by a dry ashing process using O₂ gasplasma. In this case, since the silicon concentration of thesilicon-diffused copper layer 111 on the surface thereof is high, andthe electronegativity of Si is larger than that of Cu, the Si componentof the exposed portion of the silicon-diffused copper layer 111 isoxidized, so that a silicon oxide layer 111 a is grown in thesilicon-diffused copper layer 111 in self-alignment with the via hole132 a. The silicon oxide layer 111 a serves as a copper oxidationbarrier layer.

[0129] Next, referring to FIG. 9D, the copper diffusion barrier layer109 is etched back by a dry etching process. Then, a wet strippingprocess is performed upon the insulating interlayer 110, so thatresidues of the dry etching process is completely removed.

[0130] Note that the process as illustrated in FIG. 9D can be carriedout before the process as illustrated in FIG. 9C.

[0131] Next, referring to FIG. 9E, the silicon oxide layer 111 a isetched by a plasma etching process.

[0132] Next, referring to FIG. 9F, an about 30 nm thick barrier metallayer 133 made of Ta on TaN and an about 100 nm thick seed copper layer134 a are sequentially deposited by a sputtering process on the entiresurface. Then, an about 700 nm thick copper layer 134 b is furtherdeposited by an electroplating process using the seed copper layer 134 aas a cathode electrode. Note that the copper layers 134 a and 134 b forma copper layer 134. Then, an annealing treatment is performed upon thecopper layer 134 under a N₂ atmosphere to crystallize the copper layer134 at a temperature of about 400° C. for about 30 minutes.

[0133] Next, referring to FIG. 9G, the copper layer 134 and the barriermetal layer 133 on the insulating interlayer 110 are removed by a CMPprocess.

[0134] Next, referring to FIG. 9H, the semiconductor device is cleanedand rinsed. In this case, since Cu oxide (not shown) is grown on thecopper layer 134 by pure water, the Cu oxide is removed by a solution ofoxalic acid. Then, the semiconductor device is immersed into a 1%diluted solution of benzotriazole (BTA). As a result, BTA reacts withthe Cu oxide, so that a BTA layer 134 a serving as an oxidation barrierlayer is formed on the copper layer 134. Note that the step of removingthe Cu oxide by oxalic acid can be deleted.

[0135] Next, referring to FIG. 9I, the semiconductor device is put intothe plasma CVD apparatus of FIG. 4. Then, in the plasma CVD apparatus ofFIG. 4, a heating process is performed upon the BTA layer 134 a for 2minutes under the following conditions:

[0136] temperature: 250 to 400° C.

[0137] N₂ gas: 0 to 5000 sccm

[0138] processing pressure: 0 to 20 Torr (0 to 2666.4 Pa).

[0139] As a result, the BTA layer 134 a is thermally decomposed andremoved. In this case, the copper layer 134 includes no Cu silicide.

[0140] Subsequently, in the plasma CVD apparatus of FIG. 4, a heatingprocess is performed upon the copper layer 134 for 120 seconds under thefollowing conditions:

[0141] temperature: 250 to 400° C.

[0142] SiH₄ gas: 10 to 1000 sccm

[0143] N₂ gas: 0 to 5000 sccm

[0144] processing pressure: 0 to 20 Torr (0 to 2666.4 Pa).

[0145] Thus, the copper layer 134 is converted into a silicon-diffusedcopper layer 135. Note that inorganic silane gas such as Si₂H₆ gas orSiH₂Cl₂ can be used instead of SiH₄ gas under the conditions that thetemperature is 250 to 400° C. and the processing pressure is less than20 Torr (2666 Pa), to decrease the processing time. Then, in the plasmaCVD apparatus of FIG. 4, as occasion demands, a plasma process isfurther performed upon the silicon-diffused copper layer 135 and theinsulating interlayer 110 for 3 seconds under the following conditions:

[0146] NH₃ gas: 10 to 1000 sccm

[0147] N₂ gas: 0 to 5000 sccm

[0148] processing pressure: 1 to 20 Torr (133.3 to 2666.6 Pa)

[0149] RF power: 50 to 500W.

[0150] Thus, silicon (not shown) on the surfaces of the silicon-diffusedcopper layer 135 and the insulating interlayer 110 is nitrized. Notethat the silicon on the surfaces can be etched by a plasma process usingAr gas.

[0151] Next, referring to FIG. 9J, in the plasma CVD apparatus of FIG.4, a plasma process is carried out under the following conditions:

[0152] SiH (CH₃)₃ gas: 10 to 1000 sccm

[0153] NH₃ gas: 10 to 500 sccm

[0154] He gas: 0 to 5000 sccm

[0155] processing pressure: 1 to 20 Torr (133.3 to 2666.4 Pa)

[0156] RF power: 50 to 500 W.

[0157] Thus, an about 50 nm thick copper diffusion barrier layer 136made of SiCN is deposited on the entire surface. In this case, thesilicon on an upper side of the silicon-diffused copper layer 135diffuses deeply thereinto. As a result, the Si component distributionwithin the silicon-diffused copper layer 135 is shown in FIG. 6. Thatis, the deeper the location of the silicon-diffused copper layer 135,the smaller the concentration of Si. As a result, the contactcharacteristics between the silicon-diffused copper layer 135 and thecopper diffusion barrier layer 136 can be improved. Also, the ratio ofsilicon component to copper component is caused to be lower than 8 atoms%, so that no Cu silicide having a large resistance is generated (seeCu-Si phase diagram of FIG. 7).

[0158] Note that the copper diffusion barrier layer 136 can be made ofSiC, SiCN, SiOC or organic material such as fluorocarbon polymers oramorphous carbon by a plasma process in the plasma CVD apparatus of FIG.4. Also, the copper diffusion barrier layer 136 can be a multiple layerof SiC, SiCN, SiOC and the above-mentioned organic material.

[0159] Next, referring to FIG. 9K, an about 300 nm thick insulatinginterlayer 137 made of a low-k material such as SiOF, SiOC, organicmaterial or inorganic material such as ladder-type hydrogen siloxanehaving a lower dielectric constant than that of silicon dioxide iscoated on the copper diffusion barrier layer 136. Then, an about 100 nmthick mask insulating layer 138 made of silicon dioxide is deposited bya plasma CVD process on the insulating interlayer 137. Then, ananti-reflective coating layer 139 and a photoresist layer 140 aresequentially coated on the insulating interlayer 138. Then, thephotoresist layer 140 is patterned by a photolithography process, sothat a groove (trench) 140 a is formed in the photoresist layer 140.

[0160] Next, referring to FIG. 9L, the mask insulating layer 138 and theinsulating interlayer 137 are etched by a dry etching process using thephotoresist layer 140 as a mask. Even in this case, the copper diffusionbarrier layer 136 is an incomplete etching stopper, the copper diffusionbarrier layer 136 may be also etched, although it is not shown.

[0161] Next, referring to FIG. 9M, the photoresist layer 140 and theanti-reflective layer 139 are ashed by a dry ashing process using O₂ gasplasma. In this case, since the silicon concentration of thesilicon-diffused copper layer 135 on the surface thereof is high, andthe electronegativity of Si is larger than that of Cu, the Si componentof the exposed portion of the silicon-diffused copper layer 135 isoxidized, so that a silicon oxide layer (not shown) is grown in thesilicon-diffused copper layer 135 in self-alignment with the trench 140a. The silicon oxide layer serves as a copper oxidation barrier layer.

[0162] Next, referring to FIG. 9N, the copper diffusion barrier layer136 is etched back by a dry etching process. Then, a wet strippingprocess is performed upon the mask insulating layer 138 and theinsulating interlayer 137, so that residues of the dry etching processare completely removed. Then, the silicon layer (not shown) on thesilicon-diffused copper layer 135 is etched by a plasma etching process.

[0163] Note that the process as illustrated in FIG. 9N can be carriedout before the process as illustrated in FIG. 9M.

[0164] Next, referring to FIG. 90, an about 30 nm thick barrier metallayer 141 made of Ta on TaN and an about 100 nm thick seed copper layer142 a are sequentially deposited by a sputtering process on the entiresurface. Then, an about 700 nm thick copper layer 142 b is furtherdeposited by an electroplating process using the seed copper layer 142 aas a cathode electrode. Note that the copper layers 142 a and 142 b forma copper layer 142. Then, an annealing treatment is performed upon thecopper layer 142 under a N₂ atmosphere to crystallize the copper layer142 at a temperature of about 400° C. for about 30 minutes.

[0165] Next, referring to FIG. 9P, the copper layer 142 and the barriermetal layer 141 on the insulating interlayer 138 are removed by a CMPprocess.

[0166] Next, referring to FIG. 9Q, the semiconductor device is cleanedand rinsed. In this case, since Cu oxide (not shown) is grown on thecopper layer 142 by pure water, the Cu oxide is removed by a solution ofoxalic acid. Then, the semiconductor device is immersed into a 1%diluted solution of benzotriazole (BTA). As a result, BTA reacts withthe Cu oxide, so that a BTA layer 142 a serving as an oxidation barrierlayer is formed on the copper layer 142. Note that the step of removingthe Cu oxide by oxalic acid can be deleted.

[0167] Next, referring to FIG. 9R, the semiconductor device is put intothe plasma CVD apparatus of FIG. 4. Then, in the plasma CVD apparatus ofFIG. 4, a heating process is performed upon the BTA layer 142 a for 2minutes under the following conditions:

[0168] temperature: 250 to 400° C.

[0169] N₂ gas: 0 to 5000 sccm

[0170] processing pressure: 0 to 20 Torr (0 to 2666.4 Pa).

[0171] As a result, the BTA layer 142 a is thermally decomposed andremoved. In this case, the copper layer 142 includes no Cu silicide.

[0172] Subsequently, in the plasma CVD apparatus of FIG. 4, a heatingprocess is performed upon the copper layer 142 for 120 seconds under thefollowing conditions:

[0173] temperature: 250 to 400° C.

[0174] SiH₄ gas: 10 to 100 sccm

[0175] N₂ gas: 0 to 5000 sccm

[0176] processing pressure: 0 to 20 Torr (0 to 2666.4 Pa).

[0177] Thus, the copper layer 142 is converted into a silicon-diffusedcopper layer 143. Note that inorganic silane gas such as Si₂H₆ gas orSiH₂Cl₂ can be used instead of SiH₄ gas under the conditions that thetemperature is 250 to 400° C. and the processing pressure is less than20 Torr (2666 Pa), to decrease the processing time. Then, in the plasmaCVD apparatus of FIG. 4, as occasion demands, a plasma process isfurther performed upon the silicon-diffused copper layer 143 and themask insulating layer 138 for 3 seconds under the following conditions:

[0178] NH₃ gas: 10 to 1000 sccm

[0179] N₂ gas: 0 to 5000 sccm

[0180] processing pressure: 0 to 20 Torr (0 to 2666.4 Pa)

[0181] RF power: 50 to 500W.

[0182] Thus, silicon (not shown) on the surfaces of the silicon-diffusedcopper layer 143 and the mask insulating layer 138 is nitrized. Notethat the silicon on the surfaces can be etched by a plasma process usingAr gas.

[0183] Finally, referring to FIG. 9S, in the plasma CVD apparatus ofFIG. 4, a plasma process is carried out under the following conditions:

[0184] SiH (CH₃)₃ gas: 10 to 1000 sccm

[0185] NH₃ gas: 10 to 500 sccm

[0186] He gas: 0 to 5000 sccm

[0187] processing pressure: 1 to 20 Torr (133.3 to 2666.4 Pa)

[0188] RF power: 50 to 500 W.

[0189] Thus, an about 50 nm thick copper diffusion barrier layer 144made of SiCN is deposited on the entire surface. In this case, thesilicon on an upper side of the silicon-diffused copper layer 143diffuses deeply thereinto. As a result, the Si component distributionwithin the silicon-diffused copper layer 143 is shown in FIG. 6. Thatis, the deeper the location of the silicon-diffused copper layer 143,the smaller the concentration of Si. As a result, the contactcharacteristics between the silicon-diffused copper layer 143 and thecopper diffusion barrier layer 144 can be improved. Also, the ratio ofsilicon component to copper component is caused to be lower than 8 atoms%, so that no Cu silicide having a large resistance is generated (seeCu-Si phase diagram of FIG. 7).

[0190] Note that the copper diffusion barrier layer 144 can be made ofSiC, SiCN, SiOC or organic material such as benzocycrobutene by a plasmaprocess in the plasma CVD apparatus of FIG. 4. Also, the copperdiffusion barrier layer 144 can be a multiple layer of SiC, SiCN, SiOCand the above-mentioned organic material.

[0191] Even in the method as illustrated in FIGS. 9A through 9S, sincethe three processes for each of the silicon-diffused copper layers 111,135 and 143 are sequentially carried out in the plasma CVD apparatus ofFIG. 4 without exposing the semiconductor device to the air, no oxide isgrown between the silicon-diffused copper layers 111, 135 and 143 andthe copper diffusion barrier layers 109, 136 and 144.

[0192] Also, since silicon is diffused into the entirety of thesilicon-diffused copper layers 111, 135 and 143, the migration of copperatoms within the silicon-diffused copper layers 111, 135 and 143 can besuppressed. Additionally, since the total amount of silicon in thesilicon-diffused copper layers 111, 135 and 143 is smaller than thetotal amount of silicon in the Cu silicide layer 108 of FIG. 1H, theincrease of resistance in the wiring layer, i.e., the silicon-diffusedcopper layers 111, 135 and 143 can be suppressed. Further, the oxidationof the silicon-diffused copper layers 111, 135 and 143 is suppressed,which would increase the manufacturing yield.

[0193] The modification as illustrated in FIGS. 8A and 8B using asolution of oxalic acid and a solution of benzotriazole (BTA) can alsobe applied to the method as illustrated in FIGS. 9A through 9S.

[0194] In the embodiment as illustrated in FIGS. 9A through 9S, notethat the silicon-diffused copper layer 135 can be replaced by aconventional metal layer such as the copper layer 134. In this case, itis unnecessary to convert the copper layer 134 into the silicon-diffusedcopper layer 135.

[0195]FIGS. 10A through 10V are cross-sectional views for explaining athird embodiment of the method for manufacturing a semiconductor deviceaccording to the present invention. In this case, a two-layer via firsttype dual-damascene structure is formed.

[0196] First, referring to FIG. 10A, an insulating underlayer 201 madeof silicon dioxide or the like is formed on a silicon substrate (notshown) where various semiconductor elements are formed. Then, an about50 nm thick etching stopper 202 made of SiCN is formed by a plasmaprocess on the insulating layer 201. Then, an about 300 nm thickinsulating interlayer 203 a made of a low-k material such as SiOF, SiOC,organic material or inorganic material such as ladder-type hydrogensiloxane having a lower dielectric constant than that of silicon dioxideis coated on the etching stopper 202. Then, an about 100 nm thick maskinsulating layer 203 b made of silicon dioxide is deposited by a plasmaCVD process on the insulating interlayer 203 a. Then, an anti-reflectivecoating layer 204 and a photoresist layer 205 are sequentially coated onthe mask insulating layer 203 b. Then, the photoresist layer 205 ispatterned by a photolithography process, so that a groove 205 a isformed in the photoresist layer 205.

[0197] Next, referring to FIG. 10B, the mask insulating layer 203 b andthe insulating interlayer 203 a are etched by a dry etching processusing the photoresist layer 205 as a mask.

[0198] Next, referring to FIG. 10C, the photoresist layer 205 and theanti-reflective layer 204 are ashed by a dry ashing process using O₂ gasplasma.

[0199] Next, referring to FIG. 10D, the etching stopper 202 is etchedback by a dry etching process. Then, a wet stripping process isperformed upon the mask insulating layer 203 b and the insulatinginterlayer 203 a and the insulating underlayer 201, so that residues ofthe dry etching process are completely removed.

[0200] Next, referring to FIG. 10E, an about 30 nm thick barrier metallayer 206 made of Ta on TaN and an about 100 nm thick seed copper layer207 a are sequentially deposited by a sputtering process on the entiresurface. Then, an about 700 nm thick copper layer 207 b is furtherdeposited by an electroplating process using the seed copper layer 207 aas a cathode electrode. Note that the copper layers 207 a and 207 b forma copper layer 207. Then, an annealing treatment is performed upon thecopper layer 207 under a N₂ atmosphere to crystallize the copper layer207 at a temperature of about 400° C. for about 30 minutes.

[0201] Next, referring to FIG. 10F, the copper layer 207 and the barriermetal layer 206 on the insulating interlayer 203 b are removed by a CMPprocess.

[0202] Next, referring to FIG. 10G, the semiconductor device is cleanedand rinsed. In this case, since Cu oxide (not shown) is grown on thecopper layer 207 by pure water, the Cu oxide is removed by a solution ofoxalic acid. Then, the semiconductor device is immersed into a 1%diluted solution of benzotriazole (BTA). As a result, BTA reacts withthe Cu oxide, so that a BTA layer 207 a serving as an oxidation barrierlayer is formed on the copper layer 207. Note that the step of removingthe Cu oxide by oxalic acid can be deleted.

[0203] Next, referring to FIG. 10H, the semiconductor device is put intothe plasma CVD apparatus of FIG. 4. Then, in the plasma CVD apparatus ofFIG. 4, a heating process is performed upon the BTA layer 207 a for 2minutes under the following conditions:

[0204] temperature: 250 to 400° C.

[0205] N₂ gas: 0 to 5000 sccm

[0206] processing pressure: 0 to 20 Torr (0 to 2666.4 Pa).

[0207] As a result, the BTA layer 207 a is thermally decomposed andremoved. In this case, the copper layer 207 includes no Cu silicide.

[0208] Subsequently, in the plasma CVD apparatus of FIG. 4, a heatingprocess is performed upon the copper layer 207 under the followingconditions:

[0209] temperature: 250 to 400° C.

[0210] SiH₄ gas: 10 to 1000 sccm

[0211] N₂ gas: 0 to 5000 sccm

[0212] processing pressure: 0 to 20 Torr (0 to 2666.4 Pa).

[0213] Thus, the copper layer 207 is converted into a silicon-diffusedcopper layer 221. Note that inorganic silane gas such as Si₂H₆ gas orSiH₂Cl₂ can be used instead of SiH₄ gas under the conditions that thetemperature is 250 to 400° C. and the processing pressure is less than20 Torr (2666 Pa), to decrease the processing time. Then, in the plasmaCVD apparatus of FIG. 4, as occasion demands, a plasma process isfurther performed upon the silicon-diffused copper layer 221 and themask insulating layer 203 b for 3 seconds under the followingconditions:

[0214] NH₃ gas: 10 to 1000 sccm

[0215] N₂ gas: 0 to 5000 sccm

[0216] processing pressure: 0 to 20 Torr (0 to 2666.4 Pa)

[0217] RF power: 50 to 500W.

[0218] Thus, silicon (not shown) on the surfaces of the silicon-diffusedcopper layer 221 and the mask insulating layer 203 b is nitrized. Notethat the silicon on the surfaces can be etched by a plasma process usingAr gas.

[0219] Next, referring to FIG. 101, in the plasma CVD apparatus of FIG.4, a plasma process is carried out under the following conditions:

[0220] SiH(CH₃)₃ gas: 10 to 1000 sccm

[0221] NH₃ gas: 10 to 500 sccm

[0222] He gas: 0 to 500 sccm

[0223] processing pressure: 1 to 20 Torr (199.9 to 2666.4 Pa)

[0224] RF power: 50 to 500 W.

[0225] Thus, an about 50 nm thick copper diffusion barrier layer 208made of SiCN is deposited on the entire surface. In this case, thesilicon on an upper side of the silicon-diffused copper layer 221diffuses deeply thereinto. As a result, the Si component distributionwithin the silicon-diffused copper layer 221 is shown in FIG. 6 where aninsulating underlayer (SiO₂) is in direct contact with asilicon-diffused copper layer without a barrier metal layer. That is,the deeper the location of the silicon-diffused copper layer 221, thesmaller the concentration of Si. As a result, the contactcharacteristics between the silicon-diffused copper layer 221 and thecopper diffusion barrier layer 208 can be improved. Also, the ratio ofsilicon component to copper component is caused to be lower than 8 atoms%, so that no Cu silicide having a large resistance is generated (seeCu-Si phase diagram of FIG. 7).

[0226] Next, referring to FIG. 10J, an about 400 nm thick insulatinginterlayer 209 made of silicon dioxide and an about 50 nm thick etchingstopper 210 made of SiCN are deposited on the copper diffusion barrierlayer 208. Then, an about 300 nm thick insulating interlayer 211 a madeof a low-k material such as SiOF, SiOC, organic material or inorganicmaterial such as ladder-type hydrogen siloxane having a lower dielectricconstant than that of silicon dioxide is coated on the etching stopper210. Then, an about 100 nm thick mask insulating layer 211 b made ofsilicon dioxide is deposited by a plasma CVD process on the insulatinginterlayer 211 a. Then, an anti-reflective layer 212 and a photoresistlayer 213 are sequentially coated on the insulating interlayer 211 b.Then, the photoresist layer 213 is patterned by a photolithographyprocess, so that a via hole 213 a is formed in the photoresist layer213.

[0227] Next, referring to FIG. 10K, the mask insulating layer 211 b, theinsulating interlayer 211 a, the etching stopper 210 and the insulatinginterlayer 209 are etched by a dry etching process using the photoresistlayer 213 as a mask. In this case, since the copper diffusion-barrierlayer 208 is an incomplete etching stopper, the copper diffusion barrierlayer 208 may be also etched as indicated by X.

[0228] Next, referring to FIG. 10L, the photoresist layer 213 and theanti-reflective layer 212 are ashed by a dry ashing process using O₂ gasplasma. In this case, since the silicon concentration of thesilicon-diffused copper layer 221 on the surface thereof is high, andthe electronegativity of Si is larger than that of Cu, the Si componentof the exposed portion of the silicon-diffused copper layer 221 isoxidized, so that a silicon oxide layer 221 a is grown in thesilicon-diffused copper layer 221 in self-alignment with the via hole213 a. The silicon oxide layer 221 a serves as a copper oxidationbarrier layer.

[0229] Next, referring to FIG. 10M, an anti-reflective layer 214 and aphotoresist layer 215 are sequentially coated on the entire surface.Then, the photoresist layer 215 is patterned by a photolithographyprocess so that a groove 215 a is formed in the photoresist layer 215.In this case, the anti-reflective layer 214 is buried in the via hole213 a.

[0230] Next, referring to FIG. 10N, the mask insulating layer 211 b, theinsulating interlayer 211 and the etching stopper 210 are etched by adry etching process using CF based gas plasma and using the photoresistlayer 215 as a mask.

[0231] Next, referring to FIG. 100, the photoresist layer 215 and theanti-reflective layer 214 are ashed by a dry ashing process using O₂ gasplasma. In this case, since the silicon oxide layer 221 a serves as anoxidation barrier layer, the silicon-diffused copper layer 221 is hardlyoxidized.

[0232] Next, referring to FIG. 10P, the copper diffusion barrier layer208 is etched back by a dry etching process. Then, a wet strippingprocess is performed upon the mask insulating layer 211 b, theinsulating interlayer 211 a, the etching stopper 210, the insulatinginterlayer 209, and the copper diffusion barrier layer 208, so thatresidues of the dry etching process is completely removed.

[0233] Note that the process as illustrated in FIG. 10P can be carriedout before the process as illustrated in FIG. 100.

[0234] Next, referring to FIG. 10Q, the silicon oxide layer 221 a isetched by a plasma etching process.

[0235] Next, referring to FIG. 10R, an about 30 nm thick barrier metallayer 216 made of Ta on TaN and an about 100 nm thick seed copper layer217 a are sequentially deposited by a sputtering process on the entiresurface. Then, an about 700 nm thick copper layer 217 b is furtherdeposited by an electroplating process using the seed copper layer 217 aas a cathode electrode. Note that the copper layers 217 a and 217 b forma copper layer 217. Then, an annealing treatment is performed upon thecopper layer 217 under a N₂ atmosphere to crystallize the copper layer217 at a temperature of about 400° C. for about 30 minutes.

[0236] Next, referring to FIG. 10S, the copper layer 217 and the barriermetal layer 216 on the insulating interlayer 110 are removed by a CMPprocess.

[0237] Next, referring to FIG. 10T, the semiconductor device is cleanedand rinsed. In this case, since Cu oxide (not shown) is grown on thecopper layer 217 by pure water, the Cu oxide is removed by a solution ofoxalic acid. Then, the semiconductor device is immersed into a 1%diluted solution of benzotriazole (BTA). As a result, BTA reacts withthe Cu oxide, so that a BTA layer 217 a serving as an oxidation barrierlayer is formed on the copper layer 217. Note that the step of removingthe Cu oxide by oxalic acid can be deleted.

[0238] Next, referring to FIG. 10U, the semiconductor device is put intothe plasma CVD apparatus of FIG. 4. Then, in the plasma CVD apparatus ofFIG. 4, a heating process is performed upon the BTA layer 217 a for 2minutes under the following conditions:

[0239] temperature: 250 to 400° C.

[0240] N₂ gas: 0 to 5000 sccm

[0241] processing pressure: 0 to 20 Torr (0 to 2666.4 Pa).

[0242] As a result, the BTA layer 217 a is thermally decomposed andremoved. In this case, the copper layer 217 includes no Cu silicide.

[0243] Subsequently, in the plasma CVD apparatus of FIG. 4, a heatingprocess is performed upon the copper layer 217 for 120 seconds under thefollowing conditions:

[0244] temperature: 250 to 400° C.

[0245] SiH₄ gas: 10 to 1000 sccm

[0246] N₂ gas: 0 to 4000 sccm

[0247] processing pressure: 0 to 20 Torr (0 to 2666.4 Pa).

[0248] Thus, the copper layer 217 is converted into a silicon-diffusedcopper layer 222. Note that inorganic silane gas such as Si₂H₆ gas orSiH₂Cl₂ can be used instead of SiH₄ gas under the conditions that thetemperature is 250 to 400° C. and the processing pressure is less than20 Torr (2666 Pa), to decrease the processing time. Then, in the plasmaCVD apparatus of FIG. 4, as occasion demands, a plasma process isfurther performed upon the silicon-diffused copper layer 222 and themask insulating layer 211 b for 3 seconds under the followingconditions:

[0249] NH₃ gas: 10 to 1000 sccm

[0250] N₂ gas: 0 to 5000 sccm

[0251] processing pressure: 0 to 20 Torr (0 to 2666.4 Pa)

[0252] RF power: 50 to 500W.

[0253] Thus, silicon (not shown) on the surfaces of the silicon-diffusedcopper layer 222 and the mask insulating layer 211 b is nitrized. Notethat the silicon on the surfaces can be etched by a plasma process usingAr gas.

[0254] Finally, referring to FIG. 10V, in the plasma CVD apparatus ofFIG. 4, a plasma process is carried out under the following conditions:

[0255] SiH(CH₃)₃ gas: 10 to 1000 sccm

[0256] NH₃ gas: 10 to 500 sccm

[0257] He gas: 0 to 5000 sccm

[0258] processing pressure: 1 to 20 Torr (199.9 to 2666.4 Pa)

[0259] RF power: 50 to 500 W.

[0260] Thus, an about 50 nm thick copper diffusion barrier layer 218made of SiCN is deposited on the entire surface. In this case, thesilicon on an upper side of the silicon-diffused copper layer 222diffuses deeply thereinto. As a result, the Si component distributionwithin the silicon-diffused copper layer 222 is shown in FIG. 6. Thatis, the deeper the location of the silicon-diffused copper layer 222,the smaller the concentration of Si. As a result, the contactcharacteristics between the silicon-diffused copper layer 222 and thecopper diffusion barrier layer 218 can be improved. Also, the ratio ofsilicon component to copper component is caused to be lower than 8 atoms%, so that no Cu silicide having a large resistance is generated (seeCu-Si phase diagram of FIG. 7).

[0261] Note that the copper diffusion barrier layers 208 and 218 can bemade of SiC, SiCN, SiOC or organic material such as benzocrycrobutene bya plasma process in the plasma CVD apparatus of FIG. 4. Also, each ofthe copper diffusion barrier layers 208 and 218 can be a multiple layerof SiC, SiCN, SiOC and the above-mentioned organic material.

[0262] In the method as illustrated in FIGS. 10A through 10V, theetching stopper 210 can be deleted.

[0263] Even in the method as illustrated in FIGS. 10A through 10V, sincethe three processes for each of the silicon-diffused copper layers 221and 222 are sequentially carried out in the plasma CVD apparatus of FIG.4 without exposing the semiconductor device to the air, no oxide isgrown between the silicon-diffused copper layers 221 and 222 and thecopper diffusion barrier layers 208 and 218.

[0264] Also, since silicon is diffused into the entirety of thesilicon-diffused copper layers 221 and 222, the migration of copperatoms within the silicon-diffused copper layer 221 and 222 can besuppressed. Additionally, since the total amount of silicon in thesilicon-diffused copper layers 221 and 222 is smaller than the totalamount of silicon in the Cu silicide layer 108 of FIG. 1H, the increaseof resistance in the wiring layer, i.e., the silicon-diffused copperlayers 221 and 222 can be suppressed. As a result, as shown in FIG. 11,the electromigration and stress migration resistance time was improvedas compared with cases where the layers 221 and 222 are made of pure Cuor pure Cu plus Cu silicide. Further, the oxidation of thesilicon-diffused copper layers 221 and 222 is suppressed, which wouldincrease the manufacturing yield as shown in FIG. 12.

[0265] The modification as illustrated in FIGS. 8A and 8B using asolution of oxalic acid and a solution of benzotriazole (BTA) can alsobe applied to the method as illustrated in FIGS. 10A through 10V.

[0266]FIGS. 13A through 13F are cross-sectional views for explaining afourth embodiment of the method for manufacturing a semiconductor deviceaccording to the present invention. In this case, a two-layer middlefirst type dual-damascene structure is formed.

[0267] First, the processes as illustrated in FIGS. 10A through 101 arecarried out.

[0268] Next, referring to FIG. 13A, a photoresist layer 213 is coated onthe etching stopper 210. Then, the photoresist layer 213 is patterned bya photolithography process, so that a via hole 213 a is formed in thephotoresist layer 213.

[0269] Next, referring to FIG. 13B, the etching stopper 210 is etched bya dry etching process using the photoresist layer 213 as a mask.

[0270] Next, referring to FIG. 13C, the photoresist layer 213 and theanti-reflective layer 212 are ashed by a dry ashing process using O₂ gasplasma.

[0271] Next, referring to FIG. 13D, an about 300 nm thick insulatinginterlayer 211 a made of a low-k material such as SiOF, SiOC, organicmaterial or inorganic material such as ladder-type hydrogen siloxanehaving a lower dielectric constant than that of silicon dioxide iscoated on the etching stopper 210. Then, an about 100 nm thick maskinsulating layer 211 b made of silicon dioxide is deposited by a plasmaCVD process on the insulating interlayer 211 a. Then, a photoresistlayer 215 is coated on the entire surface. Then, the photoresist layer215 is patterned by a photolithography process so that a groove 215 a isformed in the photoresist layer 215.

[0272] Next, referring to FIG. 13E, the mask insulating layer 211 b, theinsulating interlayer 211 a, the etching stopper 210 and the copperdiffusion barrier layer 208 are etched by a dry etching process using CFbased gas plasma and using the photoresist layer 215 as a mask. In thiscase, since the copper diffusion barrier layer 208 is an incompleteetching stopper, the copper diffusion barrier layer 208 may be alsoetched as indicated by X.

[0273] Next, referring to FIG. 13F, the photoresist layer 215 is ashedby a dry ashing process using O₂ gas plasma. In this case, since thesilicon oxide layer 221 a serves as an oxidation barrier layer, thesilicon-diffused copper layer 221 is hardly oxidized.

[0274] After that, the processes as illustrated in FIGS. 10P, 10Q, 10R,10S, 10T, 10U and 10V are carried out. In this case, the process asillustrated in FIG. 10P can be carried out before the process asillustrated in FIG. 13F.

[0275] In the method as illustrated in FIGS. 10A through 10I, FIGS. 13Athrough 13F and FIGS. 10P through 10V, the etching stopper 210 can bedeleted.

[0276] Even in the method as illustrated in FIGS. 10A through 10I, FIGS.13A through 13F and FIGS. 10P through 10V, since the three processes foreach of the silicon-diffused copper layers 221 and 222 are sequentiallycarried out in the plasma CVD apparatus of FIG. 4 without exposing thesemiconductor device to the air, no oxide is grown between thesilicon-diffused copper layers 221 and 222 and the copper diffusionbarrier layers 208 and 218.

[0277] Also, since silicon is diffused into the entirety of thesilicon-diffused copper layers 221 and 222, the migration of copperatoms within the silicon-diffused copper layer 221 and 222 can besuppressed. Additionally, since the total amount of silicon in thesilicon-diffused copper layers 221 and 222 is smaller than the totalamount of silicon in the Cu silicide layer 108 of FIG. 1H, the increaseof resistance in the wiring layer, i.e., the silicon-diffused copperlayers 221 and 222 can be suppressed. As a result, as shown in FIG. 11,the electromigration and stress migration resistance time was improvedas compared with cases where the layers 221 and 222 are made of pure Cuor pure Cu plus Cu silicide. Further, the oxidation of thesilicon-diffused copper layers 221 and 222 is suppressed, which wouldincrease the manufacturing yield as shown in FIG. 12.

[0278] The modification as illustrated in FIGS. 8A and 8B using asolution of oxalic acid and a solution of benzotriazole (BTA) can alsobe applied to the method as illustrated in FIGS. 10A through 10I, FIGS.13A through 13F and FIGS. 10P through 10V.

[0279] In FIG. 13A, the photoresist layer 213 is coated directly on theetching stopper 210 made of SiCN without an anti-reflective layer. Thisis because the etching stopper 210 is hydrophilic so that thewettability of an anti-reflective layer to the etching stopper 210deteriorates, thus inviting an unevenness of the anti-reflective layer.Additionally, when the anti-reflective layer is removed, the etchingstopper 210 may be damaged. On the other hand, the photoresist layer 215is coated directly on the insulating interlayer 211 b made of silicondioxide without an anti-reflective layer. This is because the insulatinginterlayer 211 b has a large recess in which a large amount of theanti-reflective layer maybe filled, thus failing in the dry etchingprocess as illustrated in FIG. 13E.

[0280] The absence of such anti-reflective layers can be compensated forby the silicon-diffused copper layer 211 which has a low reflectivitycharacteristics as shown in FIG. 14, where pure Cu has a reflectivity of32%, while silicon-diffused Cu has a reflectivity of less than 2%.

[0281] Thus, the improved photolithography processes can improve themanufacturing yield and the reliability.

[0282]FIGS. 15A through 15F are cross-sectional views for explaining afifth embodiment of the method for manufacturing a semiconductor deviceaccording to the present invention. In this case, a two-layer trenchfirst type dual-damascene structure is formed.

[0283] First, the processes as illustrated in FIGS. 10A through 10I arecarried out.

[0284] Next, referring to FIG. 15A, an about 400 nm thick insulatinginterlayer 209 made of silicon dioxide and an about 50 nm thick etchingstopper 210 made of SiCN are deposited on the copper diffusion barrierlayer 208. Then, an about 300 nm thick insulating interlayer 211 a madeof a low-k material such as SiOF, SiOC, organic material or organicmaterial such as ladder-type hydrogen siloxane having a lower dielectricconstant than that of silicon dioxide is coated on the etching stopper210. Then, an about 100 nm thick mask insulating layer 211 b made ofsilicon dioxide is deposited by a plasma CVD process on the insulatinginterlayer 211 a.

[0285] Next, referring to FIG. 15A, an anti reflective layer 214 and aphotoresist layer 215 are sequentially coated on the insulatinginterlayer 211 b. Then, the photoresist layer 215 is patterned by aphotolithography process, so that a trench (groove) 215 a is formed inthe photoresist layer 215.

[0286] Next, referring to FIG. 15B, the anti-reflective layer 214, themask insulating layer 211 b and the insulating interlayer 211 a areetched by a dry etching process using the photoresist layer 215 as amask.

[0287] Next, referring to FIG. 15C, the photoresist layer 215 and theanti-reflective layer 214 are ashed by a dry ashing process using O₂ gasplasma.

[0288] Next, referring to FIG. 15D, the etching stopper 210 is etchedback by a dry etching process.

[0289] Note that the process as illustrated in FIG. 15D can be carriedout before the process as illustrated in FIG. 15C.

[0290] Next, referring to FIG. 15E, a photoresist layer 213 is coated onthe entire surface. Then, the photoresist layer 213 is patterned by aphotolithography process, so that a via hole 213 a is formed in thephotoresist layer 213.

[0291] Next, referring to FIG. 15F, the insulating interlayer 209 isetched by a dry etching process using CF based gas plasma and using thephotoresist layer 213 as a mask. In this case, the copper diffusionbarrier layer 208 is an incomplete etching stopper, the copper diffusionbarrier layer 208 may be also etched as indicated by X.

[0292] Next, referring to FIG. 15F, the photoresist layer 213 is ashedby a dry ashing process using O₂ gas plasma. In this case, the siliconoxide layer 221 a serves as an oxidation barrier layer, thesilicon-diffused copper layer 221 is hardly oxidized.

[0293] After that, the processes as illustrated in FIGS. 10P, 10Q, 10R,10S, 10T, 10U and 10V are carried out. In this case, the process asillustrated in FIG. 10P can be carried out before the process asillustrated in FIG. 15F.

[0294] In the method as illustrated in FIGS. 10A through 10I, FIGS. 15Athrough 15F and FIGS. 10P through 10V, the etching stopper 210 can bedeleted.

[0295] Even in the method as illustrated in FIGS. 10A through 10I, FIGS.15A through 15F and FIGS. 10P through 10V, since the three processes foreach of the silicon-diffused copper layers 221 and 222 are sequentiallycarried out in the plasma CVD apparatus of FIG. 4 without exposing thesemiconductor device to the air, no oxide is grown between thesilicon-diffused copper layers 221 and 222 and the copper diffusionbarrier layers 208 and 218.

[0296] Also, since silicon is diffused into the entirety of thesilicon-diffused copper layers 221 and 222, the migration of copperatoms within the silicon-diffused copper layer 221 and 222 can besuppressed. Additionally, since the total amount of silicon in thesilicon-diffused copper layers 221 and 222 is smaller than the totalamount of silicon in the Cu silicide layer 108 of FIG. 1H, the increaseof resistance in the wiring layer, i.e., the silicon-diffused copperlayers 221 and 222 can be suppressed. As a result, as shown in FIG. 11,the electromigration and stress migration resistance time was improvedas compared with cases where the layers 221 and 222 are made of pure Cuor pure Cu plus Cu silicide. Further, the oxidation of thesilicon-diffused copper layers 221 and 222 is suppressed, which wouldincrease the manufacturing yield as shown in FIG. 12.

[0297] The modification as illustrated in FIGS. 8A and 8B using asolution of oxalic acid and a solution of benzotriazole (BTA) can alsobe applied to the method as illustrated in FIGS. 10A through 10I, FIGS.15A through 15F and FIGS. 10P through 10V.

[0298] In the above-described embodiments, the silicon-diffused copperlayers can be made of Cu alloys including at least one of Al, Ag, W, Mg,Fe, Ni, Zn, Pd, Cd, Au, Hg, Be, Pt, Zr, Ti and Sn.

[0299] Also, in the above-described embodiments, some of the insulatinginterlayers are made of silicon dioxide; however, such insulatinginterlayers can be made of a low-k material having a lower dielectricconstant than that of silicon dioxide. In this case, a mask insulatinglayer can be formed thereon. Also, the mask insulating layers such as203 b can be made of SiC, SiCN or SiOC which has a high resistancecharacteristic against the O₂ dry ashing process and its subsequent wetremoving process.

[0300] Also, in the above-described embodiments, the insulatinginterlayers made of a low-k material having a lower dielectric constantthan that of silicon dioxide are preferably made of ladder-type hydrogensiloxane. The ladder-type hydrogen siloxane is also referred to as L-Ox™(trademark of NEC Corporation). The ladder-type hydrogen siloxane has astructure as illustrated in FIG. 16A and characteristics as illustratedin FIG. 16B.

[0301] As illustrated in FIG. 16A, hydrogen atoms are two-dimensionallyand partly located on the periphery in the ladder-type hydrogensiloxane. As a result, as illustrated in FIG. 16C which shows theabsorbance characteristics of the ladder-type hydrogen siloxane, a sharpspectrum is observed at 830 nm⁻¹ and a weak spectrum is observed at 870nm⁻¹, which shows the two-dimensional arrangement of hydrogen atoms.

[0302] As illustrated in FIG. 16D which shows the density and refractiveindex characteristics of the ladder-type hydrogen siloxane, the densityand refractive index characteristics are changed in accordance with thebaking temperature. That is, when the baking temperature was smallerthan 200° C. and larger than 400° C., the refractive index was largerthan 1.40. Also, when the baking temperature was between 200° C. and400° C., the refractive index was about 1.38 to 1.40. On the other hand,when the baking temperature was smaller than 200° C., the density couldnot be observed. When the baking temperature was larger than 400° C.,the density was much larger than 1.60 g/cm³. Also, when the bakingtemperature was 200° C. and 400° C., the density was about 1.50 to 1.58g/cm³. Note that when the baking temperature is smaller than 200° C., aspectrum by a bond of Si—O at 3650 cm⁻¹ was also observed.

[0303] Note that the refractive index directly affects the dielectricconstant. In view of this, the ladder-type hydrogen siloxane used in theabove-described embodiments preferably has a density of about 1.50 to1.58 g/cm³ and preferably has a refractive index of about 1.38 to 1.40.

[0304] The features of the ladder-type hydrogen siloxane are explainednext as compared with conventional cage type hydrogen silsesquioxane(HSQ) whose structure is illustrated in FIG. 17 (see: A. Nakajima,“Coating Layers”, Semiconductor Technology Outlook, p. 432, FIG. 2,1998), with reference to FIGS. 18, 19 and 20. Note that hydrogen atomsare partly located on the periphery of the ladder-type hydrogensiloxane, while hydrogen atoms are mostly located on the periphery ofHSQ. Therefore, the hydrogen atoms in HSQ are considered to be reactiveas compared with the hydrogen atoms in the ladder-type hydrogensiloxane, which may affect the features thereof.

[0305] First, samples were prepared by coating ladder-type hydrogensiloxane or HSQ on 300 nm thick semiconductor wafers and annealing themin a N₂ atmosphere at a temperature of about 400° C. for about 30minutes.

[0306] Next, the inventors performed experiments upon theabove-mentioned samples in the plasma CVD apparatus of FIG. 4 under thefollowing conditions for converting Cu into silicon-diffused Cu:

[0307] temperature: 250 to 400° C.

[0308] SiH₄ gas: 10 to 1000 sccm

[0309] N₂ gas: 0 to 5000 sccm

[0310] pressure: 0 to 20 Torr (0 to 2666.4 Pa).

[0311] As illustrated in FIG. 18, when the SiH₄ gas irradiation time wasincreased, the thickness of HSQ was remarkably decreased. On the otherhand, even when the SiH₄ gas irradiation time was increased, thethickness of ladder-type hydrogen siloxane was not decreased.

[0312] As illustrated in FIG. 19, when the SiH₄ gas irradiation time wasincreased, the refractive index of HSQ was remarkably increased. On theother hand, even when the SiH₄ gas irradiation time was increased, therefractive index of ladder-type hydrogen siloxane was not increased.

[0313] As illustrated in FIG. 20, when the SiH₄ gas irradiation time wasincreased, the relative dielectric constant of HSQ was remarkablyincreased. On the other hand, even when the SiH₄ gas irradiation timewas increased, the relative dielectric constant of ladder-type hydrogensiloxane was not increased.

[0314] Porous ladder-type hydrogen siloxane had the same tendency asladder-type hydrogen siloxane. Thus, porous ladder-type hydrogensiloxane can be used instead of ladder-type hydrogen siloxane.

[0315] Further, the above-mentioned ladder-type hydrogen siloxane has anexcellent resistant for chemicals such as fluoric ammonium or dilutedfluoric hydrogen (HF), as compared with HSQ. For example, when immersinga semiconductor device of FIG. 21A coated with ladder-type hydrogensiloxane or HSQ into a solution of fluoric ammonium or diluted fluorichydrogen for a definite time, the etching amounts of the ladder-typehydrogen siloxane and HSQ were obtained as illustrated in FIG. 21B.

[0316] In the above-described embodiments, the mask insulating layerssuch as 203 b on the insulating interlayers such as 203 a made of alow-k material are made thin, so that the insulating interlayers such as203 a are actually exposed to SiH₄ gas. The inventors found that theparasitic capacitance of an insulating interlayer made of HSQ betweentwo adjacent wiring layers at a line/space ratio of 0.2 μm/0.2 μm wasdecreased by 2 to 3% as compared with a case where the insulatinginterlayer was made of silicon dioxide. On the other hand, the parasiticcapacitance of an insulating interlayer made of ladder-type hydrogensiloxane between two adjacent wiring layers at a line/space ratio of 0.2μm/0.2 μm was decreased by 8 to 12% as compared with a case where theinsulating interlayer was made of silicon dioxide. Also, the parasiticcapacitance of an insulating interlayer made of porous ladder-typehydrogen siloxane between two adjacent wiring layers at a line/spaceratio of 0.2 μm/0.2 μm was decreased by 15 to 20% as compared with acase where the insulating interlayer was made of silicon dioxide.

[0317] Further, when an insulating interlayer was made of methylsilsesquioxane or organic polymer including carbon atoms, Cu oxide wasgrown between a Cu (silicon-diffused copper) layer and its upper copperdiffusion barrier layer. This is because such material including carbonsatoms by the heat of the plasma CVD apparatus of FIG. 4 generateshydrocarbon gas rather than hydrogen gas so that the surface of Cu orsilicon-diffused Cu is hardly reduced. On the other hand, when aninsulating interlayer was made of ladder-type hydrogen siloxane orporous ladder-type hydrogen siloxane, no Cu oxide was grown between a Cu(silicon-diffused copper) layer and its upper copper diffusion barrierlayer. This is because such material including carbons atoms by the heatof the plasma CVD apparatus of FIG. 4 generates much hydrogen gas sothat the surface of Cu or silicon-diffused Cu is sufficiently reduced.

[0318] Additionally, each of the barrier metal layers can be a singlelayer or a multiple layer made of Ta, TaN, Ti, TiN, TaSiN and TiSiN.

[0319] Further, in the above-described embodiments, it is preferablethat the copper layers 107, 134, 142, 207 and 217 include hydrogen. Thatis, at a step for depositing the copper diffusion barrier layers 109,136, 144, 208 and 218 in the plasma CVD apparatus of FIG. 4, if there isa residual oxygen therein, oxidation occurs at the grain boundaries ofCu of the silicon-diffused copper layers 111, 135, 143, 221 and 222,thus creating Cu oxide. As a result, at a heating step using SiH₄ gas,the Cu oxide is easily converted into Cu silicide. On the other hand,when the copper layers 107, 134, 142, 207 and 217 include hydrogen sothat the silicon-diffused copper layers 111, 135, 143, 221 and 222include hydrogen, at a step for depositing the copper diffusion barrierlayers 109, 136, 144, 208 and 218 in the plasma CVD apparatus of FIG. 4,even if there is a residual oxygen therein, oxidation hardly occurs atthe grain boundaries of Cu of the silicon-diffused copper layers 111,135, 143, 221 and 222, thus creating no Cu oxide. As a result, at aheating step using SiH₄ gas, no Cu silicide is created.

[0320] The hydrogen included in the copper layers 107, 134, 142, 207 and217 was recognized by a thermal desorption spectroscopy (TDS) method ora secondary ion mass spectroscopy (SIMS) method.

[0321] Further, in order to improve the buried characteristics of thecopper layers 107, 134, 142, 207 and 217, an electroplating process fordepositing the copper layers 107, 134, 142, 207 and 217 uses a Cuplating solution including an organic component, so that the copperlayers 107, 134, 142, 207 and 217 include carbon.

[0322] As explained hereinabove, according to the present invention,since no oxide is grown between a silicon-diffused metal layer and itsupper metal diffusion barrier layer, the resistance of wiring layers canbe decreased and the manufacturing yield can be increased.

1. A semiconductor device comprising: an insulating underlayer; a firstinsulating interlayer formed on said insulating underlayer, said firstinsulating interlayer having a groove; a first silicon-diffused metallayer buried in said groove; and a first metal diffusion barrier layerformed on said first silicon-diffused metal layer and said firstinsulating interlayer.
 2. The device as set forth in claim 1, whereinsaid first insulating interlayer comprises at least one of a SiO₂ layer,a SiCN layer, a SiC layer, a SiOC layer and a low-k material layer. 3.The device as set forth in claim 2, wherein said low-k material layercomprises one of a ladder-type hydrogen siloxane layer and a porousladder-type hydrogen siloxane layer.
 4. The device as set forth in claim3, wherein said ladder-type hydrogen siloxane layer comprises an L-Ox™layer.
 5. The device as set forth in claim 3, wherein said ladder-typehydrogen siloxane layer has a density of about 1.50 g/cm³ to 1.58 g/cm³.6. The device as set forth in claim 3, wherein said ladder-type hydrogensiloxane layer has a refractive index of about 1.38 to 1.40 at awavelength of about 633 nm.
 7. The device as set forth in claim 3,further comprising a mask insulating layer made of silicon dioxideformed on the one of said ladder-type hydrogen siloxane layer and saidporous ladder-type hydrogen siloxane layer.
 8. The device as set forthin claim 1, wherein said first silicon-diffused metal layer has a largersilicon concentration near an upper side thereof than near a lower sidethereof.
 9. The device as set forth in claim 1, wherein said firstsilicon-diffused metal layer comprises a silicon-diffused copper layer.10. The device as set forth in claim 9, wherein a silicon component ofsaid silicon-diffused copper layer is less than 8 atoms %.
 11. Thedevice as set forth in claim 1, wherein said first silicon-diffusedmetal layer comprises a silicon-diffused copper alloy layer including atleast one of Al, Ag, W, Mg, Fe, Ni, Zn, Pd, Cd, Au, Hg, Be, Pt, Zr, Tiand Sn.
 12. The device as set forth in claim 1, wherein said firstsilicon-diffused metal layer includes no metal silicide.
 13. The deviceas set forth in claim 1, wherein said first silicon-diffused metal layerincludes hydrogen.
 14. The device as set forth in claim 1, wherein saidfirst silicon-diffused metal layer includes carbon.
 15. The device asset forth in claim 1, wherein said first metal diffusion barrier layercomprises at least one of a SiCN layer, a SiC layer, a SiOC layer and anorganic material layer.
 16. The device as set forth in claim 1, furthercomprising a first etching stopper between said insulating underlayerand said first insulating interlayer.
 17. The device as set forth inclaim 16, wherein said first etching stopper comprises at least one of aSiCN layer, a SiC layer, a SiOC layer and an organic material layer. 18.The device as set forth in claim 1, further comprising: a secondinsulating interlayer formed on said first metal diffusion barrierlayer, said second insulating interlayer and said first metal diffusionbarrier layer having a via hole opposing said groove of said firstinsulating interlayer; a second silicon-diffused metal layer buried insaid via hole; a second metal diffusion barrier layer formed on saidsecond silicon-diffused metal layer and said second insulatinginterlayer; a third insulating interlayer formed on said second metaldiffusion barrier layer, said third insulating interlayer and saidsecond metal diffusion barrier layer having a trench opposing said viahole; a third silicon-diffused metal layer buried in said trench; and athird metal diffusion barrier layer formed on said thirdsilicon-diffused metal layer and said third insulating interlayer. 19.The device as set forth in claim 18, wherein each of said second andthird insulating interlayers comprises at least one of a SiO₂ layer, aSiCN layer, a SiC layer, a SiOC layer and a low-k material layer. 20.The device as set forth in claim 19, wherein said low-k material layercomprises one of a ladder-type hydrogen siloxane layer and a porousladder-type hydrogen siloxane layer.
 21. The device as set forth inclaim 20, wherein said ladder-type hydrogen siloxane layer comprises anL-Ox™ layer.
 22. The device as set forth in claim 20, wherein saidladder-type hydrogen siloxane layer has a density of about 1.50 g/cm³ to1.58 g/cm³.
 23. The device as set forth in claim 20, wherein saidladder-type hydrogen siloxane layer has a refractive index of about 1.38to 1.40 at a wavelength of about 633 nm.
 24. The device as set forth inclaim 20, further comprising a mask insulating layer made of silicondioxide formed on the one of said ladder-type hydrogen siloxane layerand said porous ladder-type hydrogen siloxane layer.
 25. The device asset forth in claim 18, wherein each of said second and thirdsilicon-diffused metal layers has a larger silicon concentration near anupper side thereof than near a lower side thereof.
 26. The device as setforth in claim 18, wherein each of said second and thirdsilicon-diffused metal layers comprises a silicon-diffused copper layer.27. The device as set forth in claim 26, wherein a silicon component ofsaid silicon-diffused copper layer is less than 8 atoms %.
 28. Thedevice as set forth in claim 18, wherein each of said second and thirdsilicon-diffused metal layers comprises a silicon-diffused copper alloylayer including at least one of Al, Ag, W, Mg, Fe, Ni, Zn, Pd, Cd, Au,Hg, Be, Pt, Zr, Ti and Sn.
 29. The device as set forth in claim 18,wherein each of said second and third metal diffusion barrier layerscomprises at least one of a SiCN layer, a SiC layer, a SiOC layer and anorganic material layer.
 30. The device as set forth in claim 18, whereineach of said second and third silicon-diffused metal layers includes nometal silicide.
 31. The device as set forth in claim 18, wherein each ofsaid second and third silicon-diffused metal layers includes hydrogen.32. The device as set forth in claim 18, wherein each of said second andthird silicon-diffused metal layers includes carbon.
 33. The device asset forth in claim 1, further comprising: a second insulating interlayerformed on said first metal diffusion barrier layer, said secondinsulating interlayer and said first metal diffusion barrier layerhaving a via hole opposing said groove of said first insulatinginterlayer; a third insulating interlayer formed on said secondinsulating interlayer, said third insulating interlayer having a trenchopposing said via hole; a second silicon-diffused metal layer buried insaid trench and said via hole; and a second metal diffusion barrierlayer formed on said second silicon-diffused metal layer and said thirdinsulating interlayer.
 34. The device as set forth in claim 33, whereinsaid second insulating interlayer comprises at least one of a SiO₂layer, a SiCN layer, a SiC layer, a SiOC layer and a low-k materiallayer.
 35. The device as set forth in claim 34, wherein said low-kmaterial layer comprises one of a ladder-type hydrogen siloxane layerand a porous ladder-type hydrogen siloxane layer.
 36. The device as setforth in claim 35, wherein said ladder-type hydrogen siloxane layercomprises an L-Ox™ layer.
 37. The device as set forth in claim 35,wherein said ladder-type hydrogen siloxane layer has a density of about1.50 g/cm³ to 1.58 g/cm³.
 38. The device as set forth in claim 35,wherein said ladder-type hydrogen siloxane layer has a refractive indexof about 1.38 to 1.40 at a wavelength of about 633 nm.
 39. The device asset forth in claim 35, further comprising a mask insulating layer madeof silicon dioxide formed on the one of said ladder-type hydrogensiloxane layer and said porous ladder-type hydrogen siloxane layer. 40.The device as set forth in claim 33, wherein said secondsilicon-diffused metal layer has a larger silicon concentration near anupper side thereof than near a lower side thereof.
 41. The device as setforth in claim 33, wherein said second silicon-diffused metal layercomprises a silicon-diffused copper layer.
 42. The device as set forthin claim 41, wherein a silicon component of said silicon-diffused copperlayer is less than 8 atoms %.
 43. The device as set forth in claim 33,wherein said second silicon-diffused metal layer comprises asilicon-diffused copper alloy layer including at least one of Al, Ag, W,Mg, Fe, Ni, Zn, Pd, Cd, Au, Hg, Be, Pt, Zr, Ti and Sn.
 44. The device asset forth in claim 33, wherein said second silicon-diffused metal layerincludes no metal silicide.
 45. The device as set forth in claim 33,wherein said second silicon-diffused metal layer includes hydrogen. 46.The device as set forth in claim 33, wherein said secondsilicon-diffused metal layer includes carbon.
 47. The device as setforth in claim 33, wherein said second metal diffusion barrier layercomprises at least one of a SiCN layer, a SiC layer, a SiOC layer and anorganic material layer.
 48. The device as set forth in claim 33, furthercomprising a second etching stopper between said second and thirdinsulating interlayers, said second etching stopper having a trenchopposing said trench.
 49. The device as set forth in claim 48, where insaid second etching stopper comprises at least one of a SiCN layer, aSiC layer, a SiOC layer and an organic material layer.
 50. Asemiconductor device comprising: an insulating underlayer; a firstinsulating interlayer formed on said insulating underlayer, said firstinsulating interlayer having a groove; a first silicon-diffused metallayer including no metal silicide and buried in said groove; a firstmetal diffusion barrier layer formed on said first silicon-diffusedmetal layer and said first insulating interlayer. a second insulatinginterlayer formed on said first metal diffusion barrier layer, saidsecond insulating interlayer and said first metal diffusion barrierlayer having a via hole opposing said groove of said first insulatinginterlayer; a metal layer buried in said via hole; a second metaldiffusion barrier layer formed on said metal layer and said secondinsulating interlayer; a third insulating interlayer formed on saidsecond metal diffusion barrier layer, said third insulating interlayerand said second metal diffusion barrier layer having a trench opposingsaid via hole; a second silicon-diffused metal layer including no metalsilicide and buried in said trench; and a third metal diffusion barrierlayer formed on said second silicon-diffused metal layer and said thirdinsulating interlayer.
 51. A semiconductor device comprising: aninsulating underlayer; an insulating interlayer formed on saidinsulating underlayer, said insulating interlayer having a groove; abarrier metal layer made of at least one of Ta, TaN, Ti, TiN, TaSiN andTiSiN formed within said groove; a silicon-diffused copper layerincluding no copper silicide and buried in said groove on said barriermetal layer, said silicon-diffused copper layer having a siliconcomponent of less than 8 atoms %; and a copper diffusion barrier layermade of at least one of SiCN, SiC, SiOC and organic material and formedon said silicon-diffused copper layer and said insulating interlayer.52. A semiconductor device comprising: an insulating underlayer; a firstinsulating interlayer formed on said insulating underlayer, said firstinsulating interlayer having a groove; a first barrier metal layer madeof at least one of Ta, TaN, Ti, TiN, TaSiN and TiSiN formed within saidgroove; a first silicon-diffused copper layer including no coppersilicide and buried in said groove on said first barrier metal layer,said first silicon-diffused copper layer having a silicon component ofless than 8 atoms %; a first copper diffusion barrier layer made of atleast one of SiCN, SiC, SiOC and organic material and formed on saidfirst silicon-diffused copper layer and said first insulatinginterlayer; a second insulating interlayer formed on said first copperdiffusion barrier layer, said second insulating interlayer having a viahole opposing said groove; a second barrier metal layer made of at leastone or Ta, TaN, Ti, TiN, TaSiN and TiSiN formed within said via hole; asecond silicon-diffused copper layer including no copper silicide andburied in said via hole on said second barrier metal layer, said secondsilicon-diffused copper layer having a silicon component of less than 8atoms %; a second copper diffusion barrier layer made of at least one ofSiCN, SiC, SiOC and organic material and formed on said secondsilicon-diffused copper layer and said second insulating interlayer; athird insulating interlayer formed on said second insulating underlayer,said third insulating interlayer having a trench opposing said via hole;a third barrier metal layer made of at least one of Ta, TaN, Ti, TiN,TaSiN and TiSiN formed within said trench; a third silicon-diffusedcopper layer including no copper silicide and buried in said trench onsaid third barrier metal layer, said third silicon-diffused copper layerhaving a silicon component of less than 8 atoms %; and a third copperdiffusion barrier layer made of at least one of SiCN, SiC, SiOC andorganic material and formed on said third silicon-diffused copper layerand said third insulating interlayer.
 53. A semiconductor devicecomprising: an insulating underlayer; a first insulating interlayerformed on said insulating underlayer, said first insulating interlayerhaving a groove; a first barrier metal layer made of at least one of Ta,TaN, Ti, TiN, TaSiN and TiSiN formed within said groove; a firstsilicon-diffused copper layer including no copper silicide and buried insaid groove on said first barrier metal layer, said firstsilicon-diffused copper layer having a silicon component of less than 8atoms %; a first copper diffusion barrier layer made of at least one ofSiCN, SiC, SiOC and organic material and formed on said firstsilicon-diffused copper layer and said first insulating interlayer; asecond insulating interlayer formed on said first copper diffusionbarrier layer, said second insulating interlayer having a via holeopposing said groove; a third insulating interlayer formed on saidsecond insulating underlayer, said third insulating interlayer having atrench opposing said via hole; a second barrier metal layer made of atleast one of Ta, TaN, Ti, TiN, TaSiN and TiSiN formed within said trenchand said via hole; a second silicon-diffused copper layer including nocopper silicide and buried in said trench and said via hole on saidsecond barrier metal layer, said second silicon-diffused copper layerhaving a silicon component of less than 8 atoms %; and a second copperdiffusion barrier layer made of at least one of SiCN, SiC, SiOC andorganic material and formed on said second silicon-diffused copper layerand said third insulating interlayer.
 54. A method for manufacturing asemiconductor device, comprising the steps of: forming a first groove ina first insulating interlayer; burying a first metal layer in saidgroove; diffusing first silicon into said first metal layer from anupper surface thereof so that said first metal layer is converted into afirst silicon-diffused metal layer; and forming a first metal diffusionbarrier layer on said first silicon-diffused metal layer and said firstinsulating interlayer.
 55. The method as set forth in claim 54, whereinsaid first insulating interlayer comprises at least one of a SiO₂ layer,a SiCN layer, a SiC layer, a SiOC layer and a low-k material layer. 56.The method as set forth in claim 55, wherein said low-k material layercomprises one of a ladder-type hydrogen siloxane layer and a porousladder-type hydrogen siloxane layer.
 57. The method as set forth inclaim 56, wherein said ladder-type hydrogen siloxane layer comprises anL-Ox™ layer.
 58. The method as set forth in claim 56, wherein saidladder-type hydrogen siloxane layer has a density of about 1.50 g/cm³ to1.58 g/cm³.
 59. The method as set forth in claim 56, wherein saidladder-type hydrogen siloxane layer has a refractive index of about 1.38to 1.40 at a wavelength of about 633 nm.
 60. The method as set forth inclaim 56, further comprising a step of forming a mask insulating layermade of silicon dioxide on the one of said ladder-type hydrogen siloxanelayer and said porous ladder-type hydrogen siloxane layer.
 61. Themethod as set forth in claim 54, wherein said first silicon-diffusedmetal layer has a larger silicon concentration near an upper sidethereof than near a lower side thereof.
 62. The method as set forth inclaim 54, wherein said first silicon-diffused metal layer comprises asilicon-diffused copper layer.
 63. The method as set forth in claim 62,wherein a silicon component of said silicon-diffused copper layer isless than 8 atoms %.
 64. The method as set forth in claim 54, whereinsaid first silicon-diffused metal layer comprises a silicon-diffusedcopper alloy layer including at least one of Al, Ag, W, Mg, Fe, Ni, Zn,Pd, Cd, Au, Hg, Be, Pt, Zr, Ti and Sn.
 65. The method as set forth inclaim 54, wherein said first metal diffusion barrier layer comprises atleast one of a SiCN layer, a SiC layer, a SiOC layer and an organicmaterial layer.
 66. The method as set forth in claim 54, furthercomprising a step of forming a first etching stopper between saidinsulating underlayer and said first insulating interlayer.
 67. Themethod as set forth in claim 66, wherein said first etching stoppercomprises at least one of a SiCN layer, a SiC layer, a SiOC layer and anorganic material layer.
 68. The method as set forth in claim 54, whereinsaid first silicon diffusing step comprises the steps of: reducing firstoxide on said first metal layer; and exposing said first metal layerwith silicon-including gas so that said first metal layer is convertedinto said first silicon-diffused metal layer.
 69. The method as setforth in claim 54, wherein said first silicon diffusing step comprisesthe steps of: coating a first oxidation preventing layer on said firstmetal layer; removing said first oxidation preventing layer; andexposing said first metal layer with silicon-including gas so that saidfirst metal layer is converted into said first silicon-diffused metallayer after or when said first oxidation preventing layer is removed.70. The method as set forth in claim 69, wherein said silicon-includinggas includes inorganic silane gas.
 71. The method as set forth in claim70, wherein said inorganic silane gas includes at least one of SiH₄ gas,Si₂H₆ gas and SiH₂Cl₂ gas.
 72. The method as set forth in claim 69,wherein said first oxidation preventing layer comprises a benzotriazolelayer.
 73. The method as set forth in claim 69, further comprising astep of reducing first oxide on said first metal layer, before saidfirst oxidation preventing layer is coated.
 74. The method as set forthin claim 73, wherein said first oxide reducing step uses oxalic acid.75. The method as set forth in claim 69, wherein said first oxidationpreventing layer removing step, said first silicon-including gasexposing step and said first metal diffusion barrier layer forming stepare carried out in the same processing apparatus without exposing saidsemiconductor device to the air.
 76. The method as set forth in claim72, wherein said first oxidation preventing layer removing step iscarried out at a temperature of about 250 to 400° C.
 77. The method asset forth in claim 72, wherein said first silicon-including gas exposingstep is carried out at a temperature of about 250 to 400° C.
 78. Themethod as set forth in claim 72, wherein said first oxidation preventinglayer removing step and said first silicon-including gas exposing stepare simultaneously carried out at a temperature of about 250 to 400° C.in the same processing apparatus using said silicon-including gas. 79.The method as set forth in claim 54, wherein said first silicon-diffusedmetal layer includes no metal silicide.
 80. The method as set forth inclaim 54, wherein said first silicon-diffused metal layer includeshydrogen.
 81. The method as set forth in claim 54, wherein said firstsilicon-diffused metal layer includes carbon.
 82. The method as setforth in claim 54, further comprising the steps of: forming a secondinsulating interlayer on said first metal diffusion barrier layer, saidsecond insulating interlayer and said first metal diffusion barrierlayer having a via hole opposing said groove of said first insulatinginterlayer; burying a second metal layer in said via hole; diffusingsecond silicon into said second metal layer from an upper surfacethereof so that said second metal layer is converted into a secondsilicon-diffused metal layer; forming a second metal diffusion barrierlayer on said second silicon-diffused metal layer and said secondinsulating interlayer; forming a third insulating interlayer on saidsecond metal diffusion barrier layer, said third insulating interlayerand said second metal diffusion barrier layer having a trench opposingsaid via hole; burying a third metal layer in said trench; diffusingthird silicon into said third metal layer from an upper surface thereofso that said third metal layer is converted into a thirdsilicon-diffused metal layer; and forming a third metal diffusionbarrier layer on said third silicon-diffused metal layer and said thirdinsulating interlayer.
 83. The method as set forth in claim 82, whereineach of said second and third insulating interlayers comprises at leastone of a SiO₂ layer, a SiCN layer, a SiC layer, a SiOC layer and a low-kmaterial layer.
 84. The method as set forth in claim 83, wherein saidlow-k material layer comprises one of a ladder-type hydrogen siloxanelayer and a porous ladder-type hydrogen siloxane layer.
 85. The methodas set forth in claim 84, wherein said ladder-type hydrogen siloxanelayer comprises an L-Ox™ layer.
 86. The method as set forth in claim 84,wherein said ladder-type hydrogen siloxane layer has a density of about1.50 g/cm³ to 1.58 g/cm³.
 87. The method as set forth in claim 84,wherein said ladder-type hydrogen siloxane layer has a refractive indexof about 1.38 to 1.40 at a wavelength of about 633 nm.
 88. The method asset forth in claim 84, further comprising a forming a mask insulatinglayer made of silicon dioxide on the one of said ladder-type hydrogensiloxane layer and said porous ladder-type hydrogen siloxane layer. 89.The method as set forth in claim 82, wherein each of said second andthird silicon-diffused metal layers has a larger silicon concentrationnear an upper side thereof than near a lower side thereof.
 90. Themethod as set forth in claim 82, wherein each of said second and thirdsilicon-diffused metal layers comprises a silicon-diffused copper layer.91. The method as set forth in claim 90, wherein a silicon component ofsaid silicon-diffused copper layer is less than 8 atoms %.
 92. Themethod as set forth in claim 82, wherein each of said second and thirdsilicon-diffused metal layer comprises a silicon-diffused copper alloylayer including at least one of Al, Ag, W, Mg, Fe, Ni, Zn, Pd, Cd, Au,Hg, Be, Pt, Zr, Ti and Sn.
 93. The method as set forth in claim 82,wherein each of said second and third metal diffusion barrier layerscomprises at least one of a SiCN layer, a SiC layer, a SiOC layer and anorganic material layer.
 94. The method as set forth in claim 82, whereinsaid second silicon diffusing step comprises the steps of: reducingsecond oxide on said second metal layer; and exposing said second metallayer with silicon-including gas so that said second metal layer isconverted into said second silicon-diffused metal layer.
 95. The methodas set forth in claim 82, wherein said second silicon diffusing stepcomprises the steps of: coating a second oxidation preventing layer onsaid second metal layer; removing said second oxidation preventinglayer; and exposing said second metal layer with silicon-including gasso that said second metal layer is converted into said secondsilicon-diffused metal layer after or when said second oxidationpreventing layer is removed.
 96. The method as set forth in claim 95,wherein said silicon-including gas includes inorganic silane gas. 97.The method as set forth in claim 96, wherein said inorganic silane gasincludes at least one of SiH₄ gas, Si₂H₆ gas and SiH₂Cl₂ gas.
 98. Themethod as set forth in claim 95, wherein said second oxidationpreventing layer comprises a benzotriazole layer.
 99. The method as setforth in claim 95, further comprising a step of reducing second oxide onsaid second metal layer, before said second oxidation preventing layeris coated.
 100. The method as set forth in claim 99, wherein said secondoxide reducing step uses oxalic acid.
 101. The method as set forth inclaim 95, wherein said second oxidation preventing layer removing step,said second silicon-including gas exposing step and said second metaldiffusion barrier layer forming step are carried out in the sameprocessing apparatus without exposing said semiconductor device to theair.
 102. The method as set forth in claim 98, wherein said secondoxidation preventing layer removing step is carried out at a temperatureof about 250 to 400° C.
 103. The method as set forth in claim 98,wherein said second silicon-including gas exposing step is carried outat a temperature of about 250 to 400° C.
 104. The method as set forth inclaim 98, wherein said second oxidation preventing layer removing stepand said second silicon-including gas exposing step are simultaneouslycarried out at a temperature of about 250 to 400° C. in the sameprocessing apparatus using said silicon-including gas.
 105. The methodas set forth in claim 82, wherein said second silicon-diffused metallayer includes no metal silicide.
 106. The method as set forth in claim82, wherein said second silicon-diffused metal layer includes hydrogen.107. The method as set forth in claim 82, wherein said secondsilicon-diffused metal layer includes carbon.
 108. The method as setforth in claim 82, wherein said third silicon diffusing step comprisesthe steps of: reducing third oxide on said third metal layer; andexposing said third metal layer with silicon-including gas so that saidthird metal layer is converted into said third silicon-diffused metallayer.
 109. The method as set forth in claim 82, wherein said thirdsilicon diffusing step comprises the steps of: coating a third oxidationpreventing layer on said third metal layer; removing said thirdoxidation preventing layer; and exposing said third metal layer withsilicon-including gas so that said third metal layer is converted intosaid third silicon-diffused metal layer after or when said thirdoxidation preventing layer is removed.
 110. The method as set forth inclaim 109, wherein said silicon-including gas includes inorganic silanegas.
 111. The method as set forth in claim 110, wherein said inorganicsilane gas includes at least one of SiH₄ gas, Si₂H₆ gas and SiH₂Cl₂ gas.112. The method as set forth in claim 109, wherein said third oxidationpreventing layer comprises a benzotriazole layer.
 113. The method as setforth in claim 109, further comprising a step of reducing third oxide onsaid third metal layer, before said third oxidation preventing layer iscoated.
 114. The method as set forth in claim 113, wherein said thirdoxide reducing step uses oxalic acid.
 115. The method as set forth inclaim 109, wherein said third oxidation preventing layer removing step,said third silicon-including gas exposing step and said third metaldiffusion barrier layer forming step are carried out in the sameprocessing apparatus without exposing said semiconductor device to theair.
 116. The method as set forth in claim 112, wherein said thirdoxidation preventing layer removing step is carried out at a temperatureof about 250 to 400° C.
 117. The method as set forth in claim 112,wherein said third silicon-including gas exposing step is carried out ata temperature of about 250 to 400° C.
 118. The method as set forth inclaim 112, wherein said third oxidation preventing layer removing stepand said third silicon-including gas exposing step are simultaneouslycarried out at a temperature of about 250 to 400° C. in the sameprocessing apparatus using said silicon-including gas.
 119. The methodas set forth in claim 82, wherein said third silicon-diffused metallayer includes no metal silicide.
 120. The method as set forth in claim82, wherein said third silicon-diffused metal layer includes hydrogen.121. The method as set forth in claim 82, wherein said thirdsilicon-diffused metal layer includes carbon.
 122. The method as setforth in claim 54, further comprising the steps of: forming second andthird insulating interlayers on said first metal diffusion barrierlayer; forming a via hole in said third and second insulatinginterlayers, said via hole opposing said groove of said first insulatinginterlayer; forming a trench in said third insulating interlayer, saidtrench opposing said via hole; etching back said first metal diffusionbarrier layer using said third and second insulating layers as a mask;burying a second metal layer in said trench and via hole, after saidfirst metal diffusion barrier layer is etched back; diffusing secondsilicon into said second metal layer from an upper surface thereof sothat said second metal layer is converted into a second silicon-diffusedmetal layer; and forming a second metal diffusion barrier layer on saidsecond silicon-diffused metal layer and said third insulatinginterlayer.
 123. The method as set forth in claim 122, wherein saidsecond insulating interlayer comprises at least one of a SiO₂ layer, aSiCN layer, a SiC layer, a SiOC layer and a low-k material layer. 124.The method as set forth in claim 123, wherein said low-k material layercomprises one of a ladder-type hydrogen siloxane layer and a porousladder-type hydrogen siloxane layer.
 125. The method as set forth inclaim 124, wherein said ladder-type hydrogen siloxane layer comprises anL-Ox™ layer.
 126. The method as set forth in claim 124, wherein saidladder-type hydrogen siloxane layer has a density of about 1.50 g/cm³ to1.58 g/cm³.
 127. The method as set forth in claim 124, wherein saidladder-type hydrogen siloxane layer has a refractive index of about 1.38to 1.40 at a wavelength of about 633 nm.
 128. The method as set forth inclaim 124, further comprising a step of forming a mask insulating layermade of silicon dioxide on the one of said ladder-type hydrogen siloxanelayer and said porous ladder-type hydrogen siloxane layer.
 129. Themethod as set forth in claim 122, wherein said second silicon-diffusedmetal layer has a larger silicon concentration near an upper sidethereof than near a lower side thereof.
 130. The method as set forth inclaim 122, wherein said second silicon-diffused metal layer comprises asilicon-diffused copper layer.
 131. The method as set forth in claim130, wherein a silicon component of said silicon-diffused copper layeris less than 8 atoms %.
 132. The method as set forth in claim 122,wherein said second silicon-diffused metal layer comprises asilicon-diffused copper alloy layer including at least one of Al, Ag, W,Mg, Fe, Ni, Zn, Pd, Cd, Au, Hg, Be, Pt, Zr, Ti and Sn.
 133. The methodas set forth in claim 122, wherein said second metal diffusion barrierlayer comprises at least one of a SiCN layer, a SiC layer, a SiOC layerand an organic material layer.
 134. The method as set forth in claim122, further comprising a step of forming a second etching stopperbetween said second and third insulating interlayers, said secondetching stopper having a trench opposing said trench.
 135. The method asset forth in claim 134, wherein said second etching stopper comprises atleast one of a SiCN layer, a SiC layer, a SiOC layer and an organicmaterial layer.
 136. The method as set forth in claim 122, wherein saidsecond silicon diffusing step comprises the steps of: reducing secondoxide on said second metal layer; and exposing said second metal layerwith silicon-including gas so that said second metal layer is convertedinto said second silicon-diffused metal layer.
 137. The method as setforth in claim 122, wherein said second silicon diffusing step comprisesthe steps of: coating a second oxidation preventing layer on said secondmetal layer; removing said second oxidation preventing layer; andexposing said second metal layer with silicon-including gas so that saidsecond metal layer is converted into said second silicon-diffused metallayer after or when said second oxidation preventing layer is removed.138. The method as set forth in claim 137, wherein saidsilicon-including gas includes inorganic silane gas.
 139. The method asset forth in claim 138, wherein said inorganic silane gas includes atleast one of SiH₄ gas, Si₂₁H₆ gas and SiH₂Cl₂ gas.
 140. The method asset forth in claim 137, wherein said second oxidation preventing layercomprises a benzotriazole layer.
 141. The method as set forth in claim137, further comprising a step of reducing second oxide on said secondmetal layer, before said second oxidation preventing layer is coated.142. The method as set forth in claim 141, wherein said second oxidereducing step uses oxalic acid.
 143. The method as set forth in claim137, wherein said second oxidation preventing layer removing step, saidsecond silicon-including gas exposing step and said second metaldiffusion barrier layer forming step are carried out in the sameprocessing apparatus without exposing said semiconductor device to theair.
 144. The method as set forth in claim 140, wherein said secondoxidation preventing layer removing step is carried out at a temperatureof about 250 to 400° C.
 145. The method as set forth in claim 140,wherein said second silicon-including gas exposing step is carried outat a temperature of about 250 to 400° C.
 146. The method as set forth inclaim 140, wherein said second oxidation preventing layer removing stepand said second silicon-including gas exposing step are simultaneouslycarried out at a temperature of about 250 to 400° C. in the sameprocessing apparatus using said silicon-including gas.
 147. The methodas set forth in claim 122, wherein said second silicon-diffused metallayer includes no metal silicide.
 148. The method as set forth in claim122, wherein said second silicon-diffused metal layer includes hydrogen.149. The method as set forth in claim 122, wherein said secondsilicon-diffused metal layer includes carbon.
 150. The method as setforth in claim 54, further comprising the steps of: forming a secondinsulating interlayer on said first metal diffusion barrier layer;forming an etching stopper on said second insulating interlayer; forminga via hole in said etching stopper, said via hole opposing said grooveof said first insulating interlayer; forming a third insulatinginterlayer on said etching stopper, after said via hole is formed;forming a trench in said third insulating interlayer and a via hole insaid second insulating interlayer using said etching stopper as a mask,said trench opposing said via hole; etching back said first metaldiffusion barrier layer using said third and second insulating layers asa mask; burying a second metal layer in said trench and said via hole,after said first metal diffusion barrier layer is etched back; diffusingsecond silicon into said second metal layer from an upper surfacethereof so that said second metal is converted into a secondsilicon-diffused metal layer; and forming a second metal diffusionbarrier layer on said second silicon-diffused metal layer and said thirdinsulating interlayer.
 151. The method as set forth in claim 150,wherein said second insulating interlayer comprises at least one of aSiO₂ layer, a SiCN layer, a SiC layer, a SiOC layer and a low-k materiallayer.
 152. The method as set forth in claim 151, wherein said low-kmaterial layer comprises one of a ladder-type hydrogen siloxane layerand a porous ladder-type hydrogen siloxane layer.
 153. The method as setforth in claim 152, wherein said ladder-type hydrogen siloxane layercomprises an L-Ox™ layer.
 154. The method as set forth in claim 152,wherein said ladder-type hydrogen siloxane layer has a density of about1.50 g/cm³ to 1.58 g/cm³.
 155. The method as set forth in claim 152,wherein said ladder-type hydrogen siloxane layer has a refractive indexof about 1.38 to 1.40 at a wavelength of about 633 nm.
 156. The methodas set forth in claim 152, further comprising a step of forming a maskinsulating layer made of silicon dioxide on the one of said ladder-typehydrogen siloxane layer and said porous ladder-type hydrogen siloxanelayer.
 157. The method as set forth in claim 150, wherein said secondsilicon-diffused metal layer has a larger silicon concentration near anupper side thereof than near a lower side thereof.
 158. The method asset forth in claim 150, wherein said second silicon-diffused metal layercomprises a silicon-diffused copper layer.
 159. The method as set forthin claim 158, wherein a silicon component of said silicon-diffusedcopper layer is less than 8 atoms %.
 160. The method as set forth inclaim 150, wherein said second silicon-diffused metal layer comprises asilicon-diffused copper alloy layer including at least one of Al, Ag, W,Mg, Fe, Ni, Zn, Pd, Cd, Au, Hg, Be, Pt, Zr, Ti and Sn.
 161. The methodas set forth in claim 150, wherein said second metal diffusion barrierlayer comprises at least one of a SiCN layer, a SiC layer, a SiOC layerand an organic material layer.
 162. The method as set forth in claim150, wherein said second silicon diffusing step comprises the steps of:reducing second oxide on said second metal layer; and exposing saidsecond metal layer with silicon-including gas so that said second metallayer is converted into said second silicon-diffused metal layer. 163.The method as set forth in claim 150, wherein said second silicondiffusing step comprises the steps of: coating a second oxidationpreventing layer on said second metal layer; removing said secondoxidation preventing layer; and exposing said second metal layer withsilicon-including gas so that said second metal layer is converted intosaid second silicon-diffused metal layer after or when said secondoxidation preventing layer is removed.
 164. The method as set forth inclaim 163, wherein said silicon-including gas includes inorganic silanegas.
 165. The method as set forth in claim 164, wherein said inorganicsilane gas includes at least one of SiH₄ gas, Si₂H₆ gas and SiH₂Cl₂ gas.166. The method as set forth in claim 165, wherein said second oxidationpreventing layer comprises a benzotriazolc layer.
 167. The method as setforth in claim 165, further comprising a step of reducing second oxideon said second metal layer, before said second oxidation preventinglayer is coated.
 168. The method as set forth in claim 167, wherein saidsecond oxide reducing step uses oxalic acid.
 169. The method as setforth in claim 165, wherein said second oxidation preventing layerremoving step, said second silicon-including gas exposing step and saidsecond metal diffusion barrier layer forming step are carried out in thesame processing apparatus without exposing said semiconductor device tothe air.
 170. The method as set forth in claim 166, wherein said secondoxidation preventing layer removing step is carried out at a temperatureof about 250 to 400° C.
 171. The method as set forth in claim 166,wherein said second silicon-including gas exposing step is carried outat a temperature of about 250 to 400° C.
 172. The method as set forth inclaim 166, wherein said second oxidation preventing layer removing stepand said second silicon-including gas exposing step are simultaneouslycarried out at a temperature of about 250 to 400° C. in the sameprocessing apparatus using said silicon-including gas.
 173. The methodas set forth in claim 150, wherein said second silicon-diffused metallayer includes no metal silicide.
 174. The method as set forth in claim150, wherein said second silicon-diffused metal layer includes hydrogen.175. The method as set forth in claim 150, wherein said secondsilicon-diffused metal layer includes carbon.
 176. The method as setforth in claim 54, further comprising the steps of: forming a secondinsulating interlayer on said first metal diffusion barrier layer;forming an etching stopper on said second insulating interlayer; forminga third insulating interlayer for said etching stopper; forming a trenchin said third insulating interlayer using said etching stopper, saidtrench opposing said groove of said first insulating interlayer; etchingback said etching stopper, after said trench is perforated; forming avia hole in said second insulating interlayer using said etching stopperas a mask, said via hole opposing said groove; etching back said firstmetal diffusion barrier layer using said third and second insulatinglayers as a mask; burying a second metal layer in said trench and saidvia hole after said first metal diffusion barrier layer is etched back;diffusing second silicon into said second metal layer from an uppersurface thereof so that said second metal layer is converted into asecond silicon-diffused metal layer; and forming a second metaldiffusion barrier layer for said second silicon-diffused metal layer andsaid third insulating interlayer.
 177. The method as set forth in claim176, wherein said second insulating interlayer comprises at least one ofa SiO₂ layer, a SiCN layer, a SiC layer, a SiOC and a low-k materiallayer.
 178. The method as set forth in claim 177, wherein said low-kmaterial layer comprises one of a ladder-type hydrogen siloxane layerand a porous ladder-type hydrogen siloxane layer.
 179. The method as setforth in claim 178, wherein said ladder-type hydrogen siloxane layercomprises an L-Ox™ layer.
 180. The method as set forth in claim 178,wherein said ladder-type hydrogen siloxane layer has a density of about1.50 g/cm³ to 1.58 g/cm³.
 181. The method as set forth in claim 178,wherein said ladder-type hydrogen siloxane layer has a refractive indexof about 1.38 to 1.40 at a wavelength of about 633 nm.
 182. The methodas set forth in claim 178, further comprising a step of forming a maskinsulating layer made of silicon dioxide on the one of said ladder-typehydrogen siloxane layer and said porous ladder-type hydrogen siloxanelayer.
 183. The method as set forth in claim 176, wherein said secondsilicon-diffused metal layer has a larger silicon concentration near anupper side thereof than near a lower side thereof.
 184. The method asset forth in claim 176, wherein said second silicon-diffused metal layercomprises a silicon-diffused copper layer.
 185. The method as set forthin claim 184, wherein a silicon component of said silicon-diffusedcopper layer is less than 8 atoms %.
 186. The method as set forth inclaim 176, wherein said second silicon-diffused metal layer comprises asilicon-diffused copper alloy layer including at least one of Al, Ag, W,Mg, Fe, Ni, Zn, Pd, Cd, Au, Hg, Be, Pt, Zr, Ti and Sn.
 187. The methodas set forth in claim 176, wherein said second metal diffusion barrierlayer comprises at least one of a SiCN layer, a SiC layer, a SiOC layerand an organic material layer.
 188. The method as set forth in claim176, wherein said second silicon diffusing step comprises the steps of:reducing second oxide on said second metal layer; and exposing saidsecond metal layer with silicon-including gas so that said second metallayer is converted into said second silicon-diffused metal layer. 189.The method as set forth in claim 176, wherein said second silicondiffusing step comprises the steps of: coating a second oxidationpreventing layer on said second metal layer; removing said secondoxidation preventing layer; and exposing said second metal layer withsilicon-including gas so that said second metal layer is converted intosaid second silicon-diffused metal layer after or when said secondoxidation preventing layer is removed.
 190. The method as set forth inclaim 189, wherein said silicon-including gas includes inorganic silanegas.
 191. The method as set forth in claim 190, wherein said inorganicsilane gas includes at least one of SiH₄ gas, Si₂H₆ gas and SiH₂Cl₂ gas.192. The method as set forth in claim 189, wherein said second oxidationpreventing layer comprises a benzotriazole layer.
 193. The method as setforth in claim 189, further comprising a step of reducing second oxideon said second metal layer, before said second oxidation preventinglayer is coated.
 194. The method as set forth in claim 193, wherein saidfirst oxide reducing step uses oxalic acid.
 195. The method as set forthin claim 189, wherein said second oxidation preventing layer removingstep, said second silicon-including gas exposing step and said secondmetal diffusion barrier layer forming step are carried out in the sameprocessing apparatus without exposing said semiconductor device to theair.
 196. The method as set forth in claim 192, wherein said firstoxidation preventing layer removing step is carried out at a temperatureof about 250 to 400° C.
 197. The method as set forth in claim 192,wherein said first silicon-including gas exposing step is carried out ata temperature of about 250 to 400° C.
 198. The method as set forth inclaim 192, wherein said first oxidation preventing layer removing stepand said first silicon-including gas exposing step are simultaneouslycarried out at a temperature of about 250 to 400° C. in the sameprocessing apparatus using said silicon-including gas.
 199. The methodas set forth in claim 176, wherein said second silicon-diffused metallayer includes no metal silicide.
 200. The method as set forth in claim176, wherein said second silicon-diffused metal layer includes hydrogen.201. The method as set forth in claim 176, wherein said secondsilicon-diffused metal layer includes carbon.
 202. A method formanufacturing a semiconductor device, comprising the steps of: forming afirst groove in a first insulating interlayer; burying a first metallayer in said groove; diffusing first silicon into said first metallayer from an upper surface thereof so that said first metal layer isconverted into a first silicon-diffused metal layer including no metalsilicide; forming a first metal diffusion barrier layer on said firstsilicon-diffused metal layer and said first insulating interlayer;forming a second insulating interlayer on said first metal diffusionbarrier layer, said second insulating interlayer and said first metaldiffusion barrier layer having a via hole opposing said groove of saidfirst insulating interlayer; burying a second metal layer in said viahole; forming a second metal diffusion barrier layer on said metal layerand said second insulating interlayer; forming a third insulatinginterlayer on said second metal diffusion barrier layer, said thirdinsulating interlayer and said second metal diffusion barrier layerhaving a trench opposing said via hole; burying a third metal layer insaid trench; diffusing second silicon into said third metal layer froman upper surface thereof so that said third metal layer is convertedinto a second silicon-diffused metal layer including no metal silicide;and forming a third metal diffusion barrier layer on said secondsilicon-diffused metal layer and said third insulating interlayer. 203.A method for manufacturing a semiconductor device, comprising the stepsof: forming a groove in an insulating interlayer; forming a barriermetal layer in said groove; burying a copper layer in said groove onsaid barrier metal layer; reducing oxide on said copper layer; exposingsaid copper layer with silicon-including gas so that said copper layeris converted into a silicon-diffused copper layer including no coppersilicide, after said oxide is reduced; and forming a copper diffusionbarrier layer on said silicon-diffused copper layer and said insulatinginter layer, said oxide reducing step, said silicon-including gasexposing step and said copper diffusion barrier layer forming step beingcarried out in the same processing apparatus without exposing saidsemiconductor device to the air.
 204. A method for manufacturing asemiconductor device, comprising the steps of: forming a groove in aninsulating interlayer; forming a barrier metal layer in said groove;burying a copper layer in said groove on said barrier metal layer;coating an oxidation preventing layer made of benzotriazole on saidcopper layer; exposing said copper layer with silicon-including gas at atemperature of about 250 to 400° C. so that said copper layer isconverted into a silicon-diffused copper layer including no coppersilicide while said oxidation preventing layer is removed; and forming acopper diffusion barrier layer on said silicon-diffused copper layer andsaid insulating interlayer, said silicon-including gas exposing step andsaid copper diffusion barrier layer forming step being carried out inthe same processing apparatus without exposing said semiconductor deviceto the air.
 205. A method for manufacturing a semiconductor device,comprising the steps of: forming a groove in a first insulatinginterlayer; forming a first barrier metal layer in said groove; buryinga first copper layer in said groove on said first barrier metal layer;reducing first oxide on said first copper layer; exposing said firstcopper layer with silicon-including gas so that said first copper layeris converted into a first silicon-diffused copper layer including nocopper silicide, after said first oxide is reduced; forming a firstcopper diffusion barrier layer on said first silicon-diffused copperlayer and said first insulating interlayer; forming a second insulatinginterlayer on said first copper diffusion barrier layer; forming a viahole in said second insulating interlayer and said first copperdiffusion barrier layer, said via hole opposing said groove; forming asecond barrier metal layer in said via hole; burying a second copperlayer in said via hole on said second barrier metal layer; reducingsecond oxide on said second copper layer; exposing said second copperlayer with silicon-including gas so that said second copper layer isconverted into a second silicon-diffused copper layer including nocopper silicide, after said second oxide is reduced; forming a secondcopper diffusion barrier layer on said second silicon-diffused copperlayer and said second insulating interlayer; forming a third insulatinginterlayer on said second copper diffusion barrier layer; forming atrench in said third insulating interlayer and said second copperdiffusion barrier layer, said trench opposing said via hole; forming athird barrier metal layer in said trench; burying a third copper layerin said trench on said third barrier metal layer; reducing third oxideon said third copper layer; exposing said third copper layer withsilicon-including gas so that said third copper layer is converted intoa third silicon-diffused copper layer including no copper silicide,after said third oxide is reduced; and forming a third copper diffusionbarrier layer on said third silicon-diffused copper layer and said thirdinsulating interlayer, said first oxide reducing step, said firstsilicon-including gas exposing step and said first copper diffusionbarrier layer forming step being carried out in the same processingapparatus without exposing said semiconductor device to the air, saidsecond oxide reducing step, said second silicon-including gas exposingstep and said second copper diffusion barrier layer forming step beingcarried out in the same processing apparatus without exposing saidsemiconductor device to the air, said third oxide reducing step, saidthird silicon-including gas exposing step and said third copperdiffusion barrier layer forming step being carried out in the sameprocessing apparatus without exposing said semiconductor device to theair.
 206. A method for manufacturing a semiconductor device, comprisingthe steps of: forming a groove in a first insulating interlayer; forminga first barrier metal layer in said groove; burying a first copper layerin said groove on said first barrier metal layer; coating a firstoxidation preventing layer made of benzotriazole on said first copperlayer; exposing said first copper layer with silicon-including gas at atemperature of about 250 to 400° C. so that said first copper layer isconverted into a first silicon-diffused copper layer including no coppersilicide while said first oxidation preventing layer is removed; forminga first copper diffusion barrier layer on said first silicon-diffusedcopper layer and said first insulating interlayer; forming a secondinsulating interlayer on said first copper diffusion barrier layer;forming a via hole in said second insulating interlayer and said firstcopper diffusion barrier layer, said via hole opposing said groove;forming a second barrier metal layer in said via hole; burying a secondcopper layer in said via hole on said second barrier metal layer;coating a second oxidation preventing layer made of benzotriazole onsaid second copper layer; exposing said first copper layer withsilicon-including gas at a temperature of about 250 to 400° C. so thatsaid second copper layer is converted into a second silicon-diffusedcopper layer including no copper silicide while said second oxidationpreventing layer is removed; forming a second copper diffusion barrierlayer oil said second silicon-diffused copper layer and said secondinsulating interlayer; forming a third insulating interlayer on saidsecond copper diffusion barrier layer; forming a trench in said thirdinsulating interlayer and said second copper diffusion barrier layer,said trench opposing said via hole; forming a third barrier metal layerin said trench; burying a third copper layer in said trench on saidthird barrier metal layer; coating a third oxidation preventing layermade of benzotriazole on said third copper layer; exposing said thirdcopper layer with silicon-including gas at a temperature of about 250 to400° C. so that said third copper layer is converted into a thirdsilicon-diffused copper layer including no copper silicide while saidthird oxidation preventing layer is removed; and forming a third copperdiffusion barrier layer on said third silicon-diffused copper layer andsaid third insulating interlayer, said first silicon-including gasexposing step and said first copper diffusion barrier layer forming stepbeing carried out in the same processing apparatus without exposing saidsemiconductor device to the air, said second silicon-including gasexposing step and said second copper diffusion barrier layer formingstep being carried out in the same processing apparatus without exposingsaid semiconductor device to the air, said third silicon-including gasexposing step and said third copper diffusion barrier layer forming stepbeing carried out in the same processing apparatus without exposing saidsemiconductor device to the air.
 207. A method for manufacturing asemiconductor device, comprising the steps of: forming a groove in afirst insulating interlayer; forming a first barrier metal layer in saidgroove; burying a first copper layer in said groove on said firstbarrier metal layer; reducing first oxide on said first copper layer;exposing said first copper layer with silicon-including gas so that saidfirst copper layer is converted into a first silicon-diffused copperlayer including no copper silicide, after said first oxide is reduced;forming a first copper diffusion barrier layer on said firstsilicon-diffused copper layer and said first insulating interlayer;forming second and third insulating interlayers on said first copperdiffusion barrier layer; forming a via hole in said third and secondinsulating interlayers said via hole opposing said groove; forming atrench in said third insulating interlayer, said trench opposing saidvia hole; etching back said first copper diffusion barrier layer aftersaid trench is formed; forming a second barrier metal layer in saidtrench and said via hole on said first silicon-diffused copper layer;burying a second copper layer in said trench and said via hole on saidsecond barrier metal layer; reducing second oxide on said second copperlayer; exposing said second copper layer with silicon-including gas sothat said second copper layer is converted into a secondsilicon-diffused copper layer including no copper silicide, after saidsecond oxide is reduced; and forming a second copper diffusion barrierlayer on said second silicon-diffused copper layer and said secondinsulating interlayer, said first oxide reducing step, said firstsilicon-including gas exposing step and said first copper diffusionbarrier layer forming step being carried out in the same processingapparatus without exposing said semiconductor device to the air, saidsecond oxide reducing step, said second silicon-including gas exposingstep and said second copper diffusion barrier layer forming step beingcarried out in the same processing apparatus without exposing saidsemiconductor device to the air.
 208. A method for manufacturing asemiconductor device, comprising the steps of: forming a groove in afirst insulating interlayer; forming a first barrier metal layer in saidgroove; burying a first copper layer in said groove on said firstbarrier metal layer; coating a first oxidation preventing layer copperlayer made of benzotriazole on said first copper layer; exposing saidfirst copper layer with silicon-including gas at a temperature of about250 to 400° C. so that said first copper layer is converted into a firstsilicon-diffused copper layer including no copper silicide while saidfirst oxidation preventing layer is removed; forming a first copperdiffusion barrier layer on said first silicon-diffused copper layer andsaid first insulating interlayer; forming second and third insulatinginterlayers on said first copper diffusion barrier layer; forming a viahole in said third and second insulating interlayers said via holeopposing said groove; forming a trench in said third insulatinginterlayer, said trench opposing said via hole; etching back said firstcopper diffusion barrier layer after said trench is formed; forming asecond barrier metal layer in said trench and said via hole on saidfirst silicon-diffused copper layer; burying a second copper layer insaid trench and said via hole on said second barrier metal layer;coating a second oxidation preventing layer made of benzotriazole onsaid second copper layer; exposing said second copper layer withsilicon-including gas at a temperature of about 250 to 400° C. so thatsaid second copper layer is converted into a second silicon-diffusedcopper layer including no copper silicide while said second oxidationpreventing layer is removed; and forming a second copper diffusionbarrier layer on said second silicon-diffused copper layer and saidsecond insulating interlayer, said first silicon-including gas exposingstep and said first copper diffusion barrier layer forming step beingcarried out in the same processing apparatus without exposing saidsemiconductor device to the air, said second silicon-including gasexposing step and said second copper diffusion barrier layer formingstep being carried out in the same processing apparatus without exposingsaid semiconductor device to the air.
 209. A method for manufacturing asemiconductor device, comprising the steps of: forming a groove in afirst insulating interlayer; forming a first barrier metal layer in saidgroove; burying a first copper layer in said groove on said firstbarrier metal layer; reducing first oxide on said first copper layer;exposing said first copper layer with silicon-including gas so that saidfirst copper layer is converted into a first silicon-diffused copperlayer including no copper silicide, after said first oxide is reduced;forming a first copper diffusion barrier layer on said firstsilicon-diffused copper layer and said first insulating interlayer;forming a second insulating interlayer and an etching stopper on saidfirst copper diffusion barrier layer; forming a via hole in said etchingstopper, said via hole opposing said groove; forming a third insulatinginterlayer on said etching stopper, after said via hole is formed;forming a trench in said third insulating interlayer and a via hole insaid second insulating interlayer using said etching stopper as a mask,said trench opposing said via hole; etching back said first copperdiffusion barrier layer after said trench is formed; forming a secondbarrier metal layer in said trench and said via hole on said firstsilicon-diffused copper layer; burying a second copper layer in saidtrench and said via hole on said second barrier metal layer; reducingsecond oxide on said second copper layer; exposing said second copperlayer with silicon-including gas so that said second copper layer isconverted into a second silicon-diffused copper layer including nocopper silicide, after said second oxide is reduced; and forming asecond copper diffusion barrier layer on said second silicon-diffusedcopper layer and said second insulating interlayer, said first oxidereducing step, said first silicon-including gas exposing step and saidfirst copper diffusion barrier layer forming step being carried out inthe same processing apparatus without exposing said semiconductor deviceto the air, said second oxide reducing step, said secondsilicon-including gas exposing step and said second copper diffusionbarrier layer forming step being carried out in the same processingapparatus without exposing said semiconductor device to the air.
 210. Amethod for manufacturing a semiconductor device, comprising the stepsof: forming a groove in a first insulating interlayer; forming a firstbarrier metal layer in said groove; burying a first copper layer in saidgroove on said first barrier metal layer; coating a first oxidationpreventing layer made of benzo-triazole on said first copper layer;exposing said first copper layer with silicon-including gas so that saidfirst copper layer is converted into a first silicon-diffused copperlayer including no copper silicide while said first oxidation preventinglayer is removed; forming a first copper diffusion barrier layer on saidfirst silicon-diffused copper layer and said first insulatinginterlayer; forming a second insulating interlayer and an etchingstopper on said first copper diffusion barrier layer; forming a via holein said etching stopper, said via hole opposing said groove; forming athird insulating interlayer on said etching stopper, after said via holeis formed; forming a trench in said third insulating interlayer and avia hole in said second insulating interlayer using said etching stopperas a mask, said trench opposing said via hole; etching back said firstcopper diffusion barrier layer after said trench is formed; forming asecond barrier metal layer in said trench and said via hole on saidfirst silicon-diffused copper layer; burying a second copper layer insaid trench and said via hole on said second barrier metal layer;coating a second oxidation preventing layer made of benzotriazole onsaid second copper layer; exposing said second copper layer withsilicon-including gas at a temperature of about 250 to 400° C. so thatsaid second copper layer is converted into a second silicon-diffusedcopper layer including no copper silicide white said second oxidationpreventing layer is heated; and forming a second copper diffusionbarrier layer on said second silicon-diffused copper layer and saidsecond insulating interlayer, said first silicon-including gas exposingstep and said first copper diffusion barrier layer forming step beingcarried out in the same processing apparatus without exposing saidsemiconductor device to the air, said second silicon-including gasexposing step and said second copper diffusion barrier layer formingstep being carried out in the same processing apparatus without exposingsaid semiconductor device to the air.
 211. A method for manufacturing asemiconductor device, comprising the steps of: forming a groove in afirst insulating interlayer; forming a first barrier metal layer in saidgroove; burying a first copper layer in said groove on said firstbarrier metal layer; reducing first oxide on said first copper layer;exposing said first copper layer with silicon-including gas so that saidfirst copper layer is converted into a first silicon-diffused copperlayer including no copper silicide, after said first oxide is reduced;forming a first copper diffusion barrier layer on said firstsilicon-diffused copper layer and said first insulating interlayer;forming a second insulating interlayer, an etching stopper and a thirdinsulating interlayer on said first copper diffusion barrier layer;forming a trench in said third insulating interlayer said trenchopposing said groove; etching back said etching stopper after saidtrench is formed; forming a via hole in said second insulatinginterlayer, said via hole opposing said groove; etching back said firstcopper diffusion barrier layer after said via hole is formed; forming asecond barrier metal layer in said trench and said via hole on saidfirst silicon-diffused copper layer; burying a second copper layer insaid trench and said via hole on said second barrier metal layer;reducing second oxide on said second copper layer; exposing said secondcopper layer with silicon-including gas so that said second copper layeris converted into a second silicon-diffused copper layer including nocopper silicide, after said second oxide is reduced; and forming asecond copper diffusion barrier layer on said second silicon-diffusedcopper layer and said second insulating interlayer, said first oxidereducing step, said first silicon-including gas exposing step and saidfirst copper diffusion barrier layer forming step being carried out inthe same processing apparatus without exposing said semiconductor deviceto the air, said second oxide reducing step, said secondsilicon-including gas exposing step and said second copper diffusionbarrier layer forming step being carried out in the same processingapparatus without exposing said semiconductor device to the air.
 212. Amethod for manufacturing a semiconductor device, comprising the stepsof: forming a groove in a first insulating interlayer; forming a firstbarrier metal layer in said groove; burying a first copper layer in saidgroove on said first barrier metal layer; coating a first oxidationpreventing layer made of benzotriazole on said first copper layer;exposing said first copper layer with silicon-including gas at atemperature of about 250 to 400° C. so that said first copper layer isconverted into a first silicon-diffused copper layer including no coppersilicide while said first oxidation preventing layer is removed; forminga first copper diffusion barrier layer on said first silicon-diffusedcopper layer and said first insulating interlayer; forming a secondinsulating interlayer, an etching stopper and a third insulatinginterlayer on said first copper diffusion barrier layer; forming atrench in said third insulating interlayer said trench opposing saidgroove; etching back said etching stopper after said trench is formed;forming a via hole in said second insulating interlayer, said via holeopposing said groove; etching back said first copper diffusion barrierlayer after said via hole is formed; forming a second barrier metallayer in said trench and said via hole on said first silicon-diffusedcopper layer; burying a second copper layer in said trench and said viahole on said second barrier metal layer; coating a second oxidationpreventing layer made of benzotriazole on said second copper layer;exposing said second copper layer with silicon-including gas at atemperature of about 250 to 400° C. so that said second copper layer isconverted into a second silicon-diffused copper layer including nocopper silicide while said second oxidation preventing layer is removed;and forming a second copper diffusion barrier layer on said secondsilicon-diffused copper layer and said second insulating interlayer,said first silicon-including gas exposing step and said first copperdiffusion barrier layer forming step being carried out in the sameprocessing apparatus without exposing said semiconductor device to theair, said second silicon-including gas exposing step and said secondcopper diffusion barrier layer forming step being carried out in thesame processing apparatus without exposing said semiconductor device tothe air.